Patents by Inventor Chao-Min Wang

Chao-Min Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Manufacturing method of a circuit board structure
    Patent number: 8991043
    Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Chao-Min Wang
  • CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20130092422
    Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.
    Type: Application
    Filed: July 19, 2012
    Publication date: April 18, 2013
    Applicant: SUBTRON TECHNOLOGY CO., LTD.
    Inventor: Chao-Min Wang