Patents by Inventor Chao-Ming Tseng

Chao-Ming Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10866481
    Abstract: An electrophoretic display system and a developing method are provided. The electrophoretic display system includes an electronic device storing a control ware, a first electrophoretic display device coupled to the electronic device and a first application program interface (API) provided by the control ware. A first application program loads a first image data into the control ware, and calls the first application program interface. The control ware obtains a first driver of a first communication protocol of the first electrophoretic display device according to the first API. The control ware encapsulates the first image data with a first data encapsulating format according to the first driver. The control ware transmits the encapsulated first image data to the first electrophoretic display device according to the first communication protocol.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 15, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Chao-Ming Tseng, Yu-Hsun Kuo
  • Patent number: 10818220
    Abstract: A driving method of a display panel is provided. The display panel includes first signal lines, second signal lines, pixel structures, first signal line driving circuits, and second signal line driving circuits. The first signal line driving circuits divide the first signal lines into first signal line groups and sequentially enable the first signal lines of the first signal line groups. In one of the first signal line groups, when one first signal line adjacent to another first signal line group is enabled, the second signal line driving circuits provide a first data signal to each of the second signal lines; and when the rest of the first signal lines are enabled, the second signal line driving circuits provide a second data signal to each of the second signal lines. The first data signal and the second data signal have different waveforms to display a predetermined gray scale.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 27, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Chao-Ming Tseng, Yu-Hsun Kuo
  • Publication number: 20190369456
    Abstract: An electrophoretic display system and a developing method are provided. The electrophoretic display system includes an electronic device storing a control ware, a first electrophoretic display device coupled to the electronic device and a first application program interface (API) provided by the control ware. A first application program loads a first image data into the control ware, and calls the first application program interface. The control ware obtains a first driver of a first communication protocol of the first electrophoretic display device according to the first API. The control ware encapsulates the first image data with a first data encapsulating format according to the first driver. The control ware transmits the encapsulated first image data to the first electrophoretic display device according to the first communication protocol.
    Type: Application
    Filed: May 20, 2019
    Publication date: December 5, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Chao-Ming Tseng, Yu-Hsun Kuo
  • Publication number: 20190127573
    Abstract: A polylactic acid resin composition includes about 100 parts by weight of a polylactic acid resin, about 0.001 to about 3 parts by weight of a nucleating agent and about 3 to about 70 parts by weight of a filler. The polylactic acid resin composition can be processed into a biodegradable molded article or other product having a high impact strength and a high heat deflection temperature.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 2, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chean-Cheng SU, Chih-Pin HUNG, Shin-Luh TARNG, Chaung Chi WANG, Chao Ming TSENG, Shiu-Chih WANG
  • Publication number: 20190130814
    Abstract: A driving method of a display panel is provided. The display panel includes first signal lines, second signal lines, pixel structures, first signal line driving circuits, and second signal line driving circuits. The first signal line driving circuits divide the first signal lines into first signal line groups and sequentially enable the first signal lines of the first signal line groups. In one of the first signal line groups, when one first signal line adjacent to another first signal line group is enabled, the second signal line driving circuits provide a first data signal to each of the second signal lines; and when the rest of the first signal lines are enabled, the second signal line driving circuits provide a second data signal to each of the second signal lines. The first data signal and the second data signal have different waveforms to display a predetermined gray scale.
    Type: Application
    Filed: September 25, 2018
    Publication date: May 2, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Chao-Ming Tseng, Yu-Hsun Kuo
  • Publication number: 20110096088
    Abstract: An electrophoresis display includes a temperature sensor, a memory, a central processing unit and a display unit. The temperature sensor senses and outputs a present temperature. The memory stores a temperature characteristic table. The central processing unit is electrically coupled to the temperature sensor and the memory. The central processing unit receives the present temperature and reads the temperature characteristic table for matching the present temperature with the temperature characteristic table to obtain and output a drive level or timing. The display unit is electrically coupled to the central processing unit for receiving the drive level or timing and displaying according to the drive level.
    Type: Application
    Filed: May 5, 2010
    Publication date: April 28, 2011
    Inventors: Cheng-Hao LEE, Hsin-Chung Chen, Chao-Ming Tseng, Kuan-Fu Ting
  • Patent number: 7514771
    Abstract: A leadless lead-frame mainly includes a chip paddle and a plurality of leads. The chip paddle has chip disposal areas, and a grounding area surrounding the chip disposal area. The grounding area has a recession with a recession-bottom and a recession-wall connecting to the recession-bottom. An angle is formed between the recession-wall and the recession-bottom, and the angle is less than 90 degrees. The leads surround the chip paddle. The chip paddle has a cavity and the cavity has a cavity-bottom serving as the chip disposal area, and the depth of the cavity is equal to half of the thickness of the chip paddle.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: April 7, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao-Ming Tseng
  • Publication number: 20080088002
    Abstract: A chip package structure includes a substrate having a cavity, wherein the substrate includes a plurality of first contacts and second contacts disposed on a surface thereof, and the first contacts are located within the cavity and the second contacts are located outside the cavity. The substrate further includes a through hole located at the bottom of the cavity. A first chip is disposed in the cavity, wherein the first chip is electrically connected to the first contacts. A second chip is disposed above the cavity, wherein the second chip is electrically connected to the second contacts. A third chip is disposed in the through hole, wherein the third chip is attached to the first chip. An encapsulant is filled in the cavity to encapsulate the first chip and the second chip.
    Type: Application
    Filed: November 30, 2007
    Publication date: April 17, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao-Ming Tseng
  • Publication number: 20070164406
    Abstract: A leadless lead-frame mainly includes a chip paddle and a plurality of leads. The chip paddle has chip disposal areas, and a grounding area surrounding the chip disposal area. The grounding area has a recession with a recession-bottom and a recession-wall connecting to the recession-bottom. An angle is formed between the recession-wall and the recession-bottom, and the angle is less than 90 degrees. The leads surround the chip paddle. The chip paddle has a cavity and the cavity has a cavity-bottom serving as the chip disposal area, and the depth of the cavity is equal to half of the thickness of the chip paddle.
    Type: Application
    Filed: February 12, 2007
    Publication date: July 19, 2007
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao-Ming Tseng
  • Patent number: 7193302
    Abstract: A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The lead frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a cavity serving as a chip disposal area and a grounding area surrounding the cavity, and at least there is one recession formed on the grounding area. Besides, the chip is disposed in the cavity so that the back surface of the chip faces the chip paddle and attached onto the chip paddle via the silver paste. Moreover, the chip is electrically connected to the leads. As mentioned above, the grounding area has at least one recession formed therein, so the contact area of the leadless lead-frame with the encapsulation will be increased to enhance the attachment of the encapsulation to the leadless lead-frame.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: March 20, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao-Ming Tseng
  • Publication number: 20050218499
    Abstract: A method for manufacturing a plurality of leadless semiconductor packages is disclosed. A provided metal carrier has a plurality of packaging units with contact pads and a plurality of separating streets between the packaging units. A plurality of chips are disposed on the corresponding packaging units of the metal carrier and are electrically connected to the contact pads. A plurality of encapsulants are formed on the corresponding packaging units to encapsulate the chips but exposing the separating streets. After the metal carrier is etched away, the encapsulants connected by mold runner bars can be easily separated without sawing or punching.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Inventors: Chi-Wen Chang, Chao-Ming Tseng
  • Publication number: 20050189140
    Abstract: A chip package structure including a substrate, a first chip, a second chip, a third chip and an encapsulant is provided. The substrate has a cavity, a plurality of first contacts and second contacts disposed on a surface thereof, wherein the first contacts are located within the cavity and the second contacts are located outside the cavity, the substrate further includes a through hole located at the bottom of the cavity. The first chip is disposed in the cavity and is electrically connected to the first contacts. The second chip is disposed above the cavity and is electrically connected to the second contacts. The third chip is disposed in the through hole and is attached to the first chip. The encapsulant is filled in the cavity to encapsulate the first chip and the second chip. Moreover, the second chip, the third chip or the through hole is optional.
    Type: Application
    Filed: January 10, 2005
    Publication date: September 1, 2005
    Inventor: Chao-Ming Tseng
  • Publication number: 20050139970
    Abstract: A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The lead frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a cavity serving as a chip disposal area and a grounding area surrounding the cavity, and at least there is one recession formed on the grounding area. Besides, the chip is disposed in the cavity so that the back surface of the chip faces the chip paddle and attached onto the chip paddle via the silver paste. Moreover, the chip is electrically connected to the leads. As mentioned above, the grounding area has at least one recession formed therein, so the contact area of the leadless lead-frame with the encapsulation will be increased to enhance the attachment of the encapsulation to the leadless lead-frame.
    Type: Application
    Filed: June 28, 2004
    Publication date: June 30, 2005
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao-Ming Tseng
  • Patent number: 5827457
    Abstract: A method for manufacturing a lightweight foamed ceramic body from components comprising: (a) at least one expandable volcanic mineral; (b) at least one alkaline earth metal oxide, hydroxide, or carbonate, (c) at least one inorganic binder and (d) a foaming stabilizer, the method comprising: (1) sintering and expanding a mixture of components (a) to (d); (2) mixing the sintered and expanded material with water; (3) grinding the mixture of sintered and expanded material with water to form a ground mixture; (4) drying said ground mixture to form a dried mixture; (5) crushing said dried mixture to form a fine powder; (6) shaping said powder into a desired form to form a powder form; and (7) sintering said powder form. The ceramic material is preferably manufactured in a tunnel-type kiln. The resulting foamed ceramic is not only light in weight, but excellent in insulating properties due to its discrete cell of closed cellular structure. The foamed ceramic is useful in structural and building materials.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: October 27, 1998
    Inventor: Chao-Ming Tseng