Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.

Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.

Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through holes structure formed there through, wherein a terminal pads are formed under the through holes structure and the substrate includes a conductive trace formed on a lower surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die and the through holes structure. Conductive bumps are coupled to the terminal pads. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination.

Abstract: The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, traces formed within the substrate; a first die disposed within the die receiving cavity; a first dielectric layer formed on the first die and the substrate; a first re-distribution layer (RDL) formed on the first dielectric layer, wherein the first RDL is coupled to the first die and the traces; a second dielectric layer formed over the first RDL; a second die disposed on the second dielectric layer; a third dielectric layer formed over the second dielectric layer and the second die; a second RDL formed on the third dielectric layer, wherein the second RDL is coupled to the second die and the first RDL; a forth dielectric layer formed over the second RDL; a third die formed over the forth dielectric layer and coupled to the second RDL; a fifth dielectric layer formed around the third die; and a plastic c

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

Abstract: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

Abstract: The present invention discloses a structure of wafer level packaging. To use the elastic materials with low k dielectric constant and larger elongation properties as dielectric layers materials used for build up layers of semiconductor device packaging, it can improve the reliability, especially in the board level temperature cycling test. In principle, the elastic dielectric layers can absorb the stress due to CTE (Coefficient of Thermal Expansion) mismatching issue.

Abstract: A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.

Abstract: A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.

Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.