Patents by Inventor Chao-Ping Chuang

Chao-Ping Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160021448
    Abstract: A microphone system includes an acoustic control unit and a microphone unit. The acoustic control unit transmits a clock signal and receives an acoustic audio signal and determines whether or not the acoustic audio signal is a valid audio data. The microphone unit receives the clock signal from the acoustic control unit and transmits the acoustic audio signal captured by the microphone unit to the acoustic control unit. Before the acoustic audio signal is determined as the valid audio data, the acoustic control unit transmits the clock signal which is turned on and off repeatedly with an ON duration and an OFF duration.
    Type: Application
    Filed: November 5, 2014
    Publication date: January 21, 2016
    Inventors: Chien-Wen Peng, Chao-Ping Chuang
  • Publication number: 20050204089
    Abstract: A method and related system for accessing low pin count (LPC) memory or firmware memory includes selecting an LPC memory or a firmware memory according to an input signal, recording an address of the selected memory, determining weather to read or write data according to the input signal, and accessing data accordingly.
    Type: Application
    Filed: June 13, 2004
    Publication date: September 15, 2005
    Inventors: Chao-Ping Chuang, Jen-Chin Chan
  • Publication number: 20050125622
    Abstract: When the memory device receives address information and byte information M, the memory device continuously provides M bytes corresponding to M addresses following an address assigned in the address information. The memory device includes: an address calculation module, an address buffer, a decoding module, a plurality of memory units and output buffers. Each output buffer is capable of receiving data of two units and sequentially outputting the data. When the address calculation module stores an address in the address buffer, the decoding module makes cells corresponding to the address simultaneously output data to the output buffers, such that the output buffers sequentially output data of respective unit. The address calculation module starts to count the next address, such that when the output buffer finishes outputting, the next address is already stored in the address buffer, and the decoding module has already made units corresponding to the next address output data.
    Type: Application
    Filed: May 28, 2004
    Publication date: June 9, 2005
    Inventors: Chao-Ping Chuang, Jen-Chin Chan