Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: Method of successively depositing a multi-film is disclosed. An electric charge removing process is performed after a deposition process of the last film of the multi-film or between the two neighboring film deposition processes. The electric charge removing process includes introducing an inert gas into a reaction chamber of the deposition system and pumping out the inert gas from the reaction chamber.

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: A method for gap filling between metal-metal lines is provided so that a first dielectric layer forms on a surface and side wall of a plurality of metal lines thereon which is called partially HDP deposition. Then, a portion of the first dielectric layer is removed by a high-density plasma with Ar/O2 to sputter so that a portion of side wall of metal lines is exposed. Afterwards, a second dielectric layer is formed on the first dielectric layer by a method of high density plasma oxide deposition so that the metal lines are completely covered.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: An apparatus for depositing an insulation layer in a trench. A wafer loader is used to load a wafer having a trench. A first HDP-CVD chamber adjoins the wafer loader, where the first HDP-CVD chamber is used to deposit a first insulation layer in the trench, and the first trench retains an opening. A vapor-etching chamber adjoins the first HDP-CVD chamber. The vapor-etching chamber is used to remove part of the first insulation layer to leave a remaining first insulation layer at the bottom of the trench and expose the sidewall of the trench above the remaining first insulation layer. A second HDP-CVD chamber adjoins the vapor-etching chamber, where the second HDP-CVD chamber fills the trench by depositing a second insulation layer. A wafer unloader adjoins the second HDP-CVD chamber.