Patents by Inventor Chao-Sheng Lin

Chao-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240131808
    Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 25, 2024
    Inventors: TENG-YEN WANG, SHUN-SHENG KO, MIAO-CHANG WU, TUNG-YING LIN, CHAO-HONG HSU
  • Patent number: 11924722
    Abstract: An information converting method and a system thereof are configured to convert a first information into a second information. An information obtaining step is performed to obtain the first information corresponding to a first communication protocol and transmit the first information to a converter. The first information includes a first access layer sub-information and an upper-layer protocol sub-information. A first access layer removing step is performed to drive the converter to remove the first access layer sub-information from the first information according to a converting process. A second access layer adding step is performed to drive the converter to add a second access layer sub-information corresponding to a second communication protocol to the first information and combine the second access layer sub-information with the upper-layer protocol sub-information according to the converting process, so that the first information is converted into the second information.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: March 5, 2024
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Chun-Nan Chen, Yuan-Ruei Huang, Chao-Sheng Lin
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Publication number: 20220312162
    Abstract: An information converting method and a system thereof are configured to convert a first information into a second information. An information obtaining step is performed to obtain the first information corresponding to a first communication protocol and transmit the first information to a converter. The first information includes a first access layer sub-information and an upper-layer protocol sub-information. A first access layer removing step is performed to drive the converter to remove the first access layer sub-information from the first information according to a converting process. A second access layer adding step is performed to drive the converter to add a second access layer sub-information corresponding to a second communication protocol to the first information and combine the second access layer sub-information with the upper-layer protocol sub-information according to the converting process, so that the first information is converted into the second information.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 29, 2022
    Inventors: Chun-Nan CHEN, Yuan-Ruei HUANG, Chao-Sheng LIN
  • Publication number: 20070042556
    Abstract: A method of fabricating a metal oxide semiconductor transistor is described. A substrate having device isolation structures thereon is provided. A stack gate structure is formed over the substrate. An etching stop layer is formed over the substrate to cover the stack gate structure, the substrate and the device isolation structures. Thereafter, spacers are formed on the sidewalls of the stack gate structure. The spacers and the etching stop layer have different etching selectivity. A source region and a drain region are formed in the substrate beside the spacer on each side of the stack gate structure using the stack gate structure and the spacers as a mask. Then, the spacers are removed and a lightly doped region and a lightly doped drain region are formed in the substrate on each side of the stack gate structure using the stack gate structure as a mask.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 22, 2007
    Inventor: Chao-Sheng Lin
  • Patent number: 6455389
    Abstract: This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. The present invention uses a liner, whose surface is treated, and a spacer, which is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. This prevents by-product ions from moving from the spacer to other regions by using actions in diffusion and drift to affect the voltage stability of the semiconductor device after the current is connected. This defect will further affect qualities of the semiconductor device.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: September 24, 2002
    Inventors: Kuo-Tai Huang, Chao-Sheng Lin, Li-Wei Cheng
  • Patent number: D912500
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 9, 2021
    Assignee: FIVETECH TECHNOLOGY INC.
    Inventors: Ting-Jui Wang, Chao-Sheng Lin