Abstract: A semiconductor memory device featuring redundant output switches for routing all data transactions to corresponding redundant columns instead of defective columns. The memory device includes an ordinary decoder and an ordinary memory cell array having a plurality of ordinary columns. The ordinary decoder is provided for decoding an address signal to drive one of the ordinary memory cells in the ordinary columns. The memory device also includes a redundant memory cell array, a redundant decoder and a redundant switch circuit. The redundant memory cell array has a plurality of redundant columns adapted to replace defective columns in the ordinary columns. The redundant decoder has a plurality of redundant decode circuits, in which a redundant decode circuit provides a redundant decode signal to the corresponding redundant column for driving it.

Abstract: A semiconductor memory device featuring redundant output switches for routing all data transactions to corresponding redundant columns instead of defective columns. The memory device includes an ordinary decoder and an ordinary memory cell array having a plurality of ordinary columns. The ordinary decoder is provided for decoding an address signal to drive one of the ordinary memory cells in the ordinary columns. The memory device also includes a redundant memory cell array, a redundant decoder and a redundant switch circuit The redundant memory cell array has a plurality of redundant columns adapted to replace defective columns in the ordinary columns. The redundant decoder has a plurality of redundant decode circuits, in which a redundant decode circuit provides a redundant decode signal to the corresponding redundant column for driving it.

Abstract: A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the repairing process, the fuses connected with the pull-transistors coupled to the defect bit lines are disconnected, therefore cutting the leakage current completely. The standby leakage current can be reduced such that the SRAM can pass the standby current test and the yield is improved.

Abstract: Zigzag scanning is one of the key techniques in image data compression. An efficient method and device is needed in some dedicated cases. In the present invention, a fixed delay is performed between DCT and zigzag scan to make the present invention simple. The present invention requires only half the number of transistors compared to the prior art.

Abstract: A method of monitoring ion contamination in integrated circuits is disclosed. The method makes use of the electric field induced by bias voltages and the heating circuit provided in the integrated circuit to raise temperature in order to drive mobile ions into or out of the gate oxide layer of a MOS transistor. Then, the threshold voltages of the MOS transistor under different ion contamination are measured respectively. The ion contamination induced whether in front-end process or back-end process can be detected properly.

Abstract: In an SRAM for SNM measurement, the original word line of the SRAM cell for SNM measurement is divided into two segments for SNM measurement, wherein one segment is connected to the first node of the SRAM cell for SNM measurement, another segment is connected to the second node of the SRAM cell for SNM measurement. In addition, an adjacent word line adjacent to the SRAM cell for SNM measurement is connected to the SRAM cell for SNM measurement to form the word line of the SRAM cell. Therefore, the process of the SRAM for SNM measurement can be improved only by modifying the mask for the layout of the polysilicon layers in conventional ones.

Abstract: A method of testing for SRAM pull-down transistor sub-threshold leakage is disclosed. The method according to the present invention can detect the problem of changes in store state resulting form sub-threshold leakage current flow through the parasitic resistor in SRAM, and therefore provides an advantageous way for the manufacturer to eliminate the defective products and thereby improve the reliability of SRAM.