Abstract: Disclosed is a driving circuit, a display panel and a display device. The driving circuit includes a plurality of cascaded driving units, where a first staged driving unit includes a forward and backward scan control module, a node signal control module, an output control module, a first voltage stabilizing module, a first pull-down module, a second pull-down module and an electrical leakage control module. The electrical leakage control module is configured to maintain a voltage level of an output signal of the forward and backward scan control module.

Abstract: A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively.

Abstract: Embodiments of the disclosure pertain to a system for transferring an optical signal from one photonics chip or integrated circuit (PIC) to another. The system includes a first PIC having (i) an optical emitter or optical transmission mechanism and (ii) a focusing mirror thereon, and a second PIC having an optical receiver and a reflecting mirror thereon. The reflecting mirror is configured to reflect light transmitted by the optical emitter or optical transmission mechanism back to the first PIC. The focusing mirror is configured to (i) further reflect the light reflected by the reflecting mirror and (ii) focus the further reflected light on the optical receiver. Methods of using and manufacturing the system are also disclosed.

Abstract: A pixel circuit and a display panel related to the field of display technology are provided. The pixel circuit and the display panel include a driving transistor, a first transistor, a second transistor, a first capacitor, and a second capacitor. The pixel circuit and the display panel, before emitting light, preset an electric potential of a gate, a drain, and a source of a driving transistor. As a result, a light-emitting current passing the driving transistor can be immune from a threshold voltage of the driving transistor during luminescence, further eliminating an ununiform luminescence phenomenon due to a drift of the threshold voltage.

Abstract: A gate driver on array (GOA) circuit, a display panel and a display device are provided. The GOA circuit includes m cascaded GOA units. An nth-stage GOA unit includes a second feedback module. The second feedback module, electrically connected to the second node of the nth-stage GOA unit, a first node of the (n?1)th-stage GOA unit, the clock signal of the (n+1)th-stage GOA unit, a gate driving signal of the nth-stage GOA unit and the constant low voltage signal, to pull down voltage applied on a second node of the nth-stage GOA unit. The one-way feedback could achieve the linear design more easily, raise the circuit stability, and thus the GOA circuit could be integrated in the display panel more easily to achieve the design of placing the GOA circuit in the active area.

Abstract: The present invention provides an array substrate, a manufacturing method thereof, and a display panel. Orthographic projections of channel layers of two types of thin film transistors in a design of a driving circuit on the array substrate at least partially overlap, that is, two thin film transistors are stacked on top of each other, thereby facilitating a narrow border design of the display panel. In addition, a channel layer of one of the thin film transistors is an amorphous oxide semiconductor layer, which can reduce node leakage in the driving circuit, which is conducive to improving circuit stability and reducing power consumption.

Abstract: A gate driver on array (GOA) circuit, a display panel and a display device are provided. The GOA circuit includes m cascaded GOA units. An nth-stage GOA unit includes a second feedback module. The second feedback module, electrically connected to the second node of the nth-stage GOA unit, a first node of the (n?1)th-stage GOA unit, the clock signal of the (n+1)th-stage GOA unit, a gate driving signal of the nth-stage GOA unit and the constant low voltage signal, to pull down voltage applied on a second node of the nth-stage GOA unit. The one-way feedback could achieve the linear design more easily, raise the circuit stability, and thus the GOA circuit could be integrated in the display panel more easily to achieve the design of placing the GOA circuit in the active area.

Abstract: The present application discloses a processing method, device, equipment and storage medium of a loop instruction, and relates to the fields of voice and chips. A specific embodiment is: acquiring a computer program including a first loop body, where the first loop body is generated according to a second loop body in a software code to be compiled, the first loop body includes a plurality of first loop instructions, the plurality of first loop instructions can be identified by a hardware structure of a computer device; in the case that the first loop body is detected, determining loop parameters of the first loop body according to the plurality of first loop instructions; acquiring the plurality of first loop instructions according to the loop parameters of the first loop body; executing the plurality of first loop instructions.

Abstract: The disclosure provides a method and an apparatus for allocating memory, and an electronic device. Multiple frames of speech data are received and input to a neural network model. The neural network model is configured to ask for multiple data tensors when processing the multiple frames of speech data, and the multiple data tensors share a common memory.

Abstract: A data processing method for a neural network accelerator, an electronic device and a storage medium are provided. The technical solution includes: obtaining data to be processed and an operation to be executed; obtaining a real-number full-connection operation corresponding to the operation to be executed; and performing the real-number full-connection operation on the data based on a real-number full-connection unit of the neural network accelerator to obtain a result of the operation to be executed for the data.

Abstract: The disclosure provides a method for multiply-add operations for a neural network. The method includes: determining types of respective pieces of data to be calculated based on a multiply-add operation request; in a condition of the type of each piece of the data to be calculated is a type of single-precision floating point, compressing mantissa of each pieces of the data to be calculated to obtain each compressed mantissa; splitting each compressed mantissa according to a preset rule and determining high digits and low digits of the compressed mantissa; and performing a multiply-add operation on each compressed mantissa based on the high digits and low digits of the compressed mantissa.

Abstract: Embodiments pertain to an optical transmitter, including a thermally unregulated light emitting device and a sloped or graded passband filter. The light emitting device is configured to receive a bias current and output an optical signal within a wavelength band. The sloped or graded passband filter is configured to attenuate an output power of the optical signal in the wavelength band. The light emitting device has a maximum bias current limit, a maximum operating temperature limit, and maximum and minimum output power limits, and the sloped or graded passband filter has an insertion loss in the wavelength band that decreases as the light emitting device temperature increases and/or the optical signal wavelength increases within the wavelength band. The attenuated optical signal is within the maximum and minimum output power limits when the bias current is at or below the maximum bias current limit and the light emitting device outputs the optical signal at or below the maximum operating temperature limit.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a base substrate having an opening; and a first gate layer formed in the opening. In the first gate layer closes a top of the opening and the first gate layer includes at least one void. The semiconductor structure further includes a second gate layer formed on the first gate layer. An atomic radius of the material of the second gate layer is smaller than gaps among atoms of the material of the first gate layer and the void is filled by atoms of one of the material of the first gate layer and the material of the second gate layer.

Abstract: The present application discloses a voice processing system and method, an electronic device and a readable storage medium, which relates to the field of voice processing technologies. The voice processing system includes: a neural-network processing unit (NPU) and an RISC-V processor; wherein the RISC-V processor includes predefined NPU instructions, and the RISC-V processor is configured to send the NPU instructions to the NPU to cause the NPU to perform corresponding neural network computation; the NPU includes a memory unit and a computing unit, and the memory unit includes a plurality of storage groups; the computing unit is configured to execute one of main computation, special computation, auxiliary computation and complex instruction set computing (CISC) control according to the received NPU instructions.

Abstract: A method of driving an electronic paper display apparatus includes: providing a preprocessing signal in the first pulse signal to the first electrode in the display stage of the first image display stage, so that the first particles and the third particles are mixed, and the first particles and the third particles are closer to a display side of the display apparatus than the second particles; and providing a first sub-pulse signal in the first pulse signal to the first electrode in the display stage of the first image display stage after providing the preprocessing signal, so that the third particles are closer to the display side of the display apparatus than the first particles and the second particles and the microcup displays the third color.

Abstract: A display driving circuit is provided. The display driving circuit includes a multi-stage driving unit, and each stage of the driving unit includes a pull-up control unit and a pull-up unit. The pull-up unit is electrically connected to a second high voltage signal input terminal, so that high voltage signal input from the second high voltage signal input terminal is directly transmitted to a cascade signal output terminal through the pull-up unit, which further enables the display driving circuit to output a high voltage driving signal while a gate of a thin film transistor inside the display driving circuit is kept at low voltage.

Abstract: An embodiment of the present invention discloses an array substrate, a method of fabricating the same, and a display panel. Compared with the conventional technology, the present invention combines a sensing material with thin film transistors to prepare a sensing layer on the thin film transistors, and since the thin film transistors can be formed by a large-area preparation, the sensors can be formed by a large-area preparation accordingly, thereby improving a performance of the sensors and reducing the production cost of the sensors.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having an opening and forming a first gate layer in the opening. The first gate layer closes a top of the opening and includes a void. The method also includes forming a second gate layer on the first gate layer. An atomic radius of a material of the second gate layer is smaller than gaps among the atoms of the material of the first gate layer. Further, the method includes performing a thermal annealing process to cause atoms of the material of the second layer to pass through the first gate layer to fill the void.

Abstract: The present invention provides an array substrate, a manufacturing method thereof, and a display panel. Orthographic projections of channel layers of two types of thin film transistors in a design of a driving circuit on the array substrate at least partially overlap, that is, two thin film transistors are stacked on top of each other, thereby facilitating a narrow border design of the display panel. In addition, a channel layer of one of the thin film transistors is an amorphous oxide semiconductor layer, which can reduce node leakage in the driving circuit, which is conducive to improving circuit stability and reducing power consumption.

Abstract: A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively.