Patents by Inventor Chao Tsai

Chao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250070011
    Abstract: A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.
    Type: Application
    Filed: January 2, 2024
    Publication date: February 27, 2025
    Inventors: Chih-Chao Chou, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12237233
    Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20250062225
    Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Inventors: Ashim Dutta, Chih-Chao Yang, Ailian Zhao, Wu-Chang Tsai
  • Publication number: 20250046700
    Abstract: A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source/drain region, a second source/drain region, a second bond pad electrically connecting to the first source/drain region, and a third bond pad electrically connecting to the second source/drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 6, 2025
    Inventors: Chih-Chao Chou, Cheng-Chi Chuang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12216157
    Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: February 4, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
  • Publication number: 20240391052
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yi-Fam SHIU, Cheng-Chao TSAI, Cheng-Lung WU, Chih-Hung HUANG, Jiun-Rong PAI
  • Patent number: 12083648
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fam Shiu, Cheng-Chao Tsai, Cheng-Lung Wu, Chih-Hung Huang, Jiun-Rong Pai
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Publication number: 20230039611
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Yi-Fam SHIU, Cheng-Chao TSAI, Cheng-Lung WU, Chih-Hung HUANG, Jiun-Rong PAI
  • Publication number: 20210298203
    Abstract: An automotive electronic device durable in an automotive environment of at least 95° C. includes a bottom cover, a circuit board and a heatsink casing. The circuit board is installed on the bottom cover. The heatsink casing is assembled with the bottom cover, and covers the circuit board between the heatsink casing and the bottom cover. The heatsink casing includes an outer surface, a plurality of long fins and a plurality of side fins. The long fins are arranged on the outer surface along a first direction. Two adjacent ones of the long fins have a distance at least greater than 8 mm. The side fins are arranged on an edge of the outer surface along a second direction, and connected to one of the long fins.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 23, 2021
    Inventors: CHAO-TSAI CHUNG, PO-LIN LIN, SHU-TING CHAN
  • Publication number: 20190347833
    Abstract: A head-mounted electronic device including a head-mounted frame, a lens, a photosensitive element, a projector, an optical element, a processor, and a memory is provided. The lens and the projector are disposed on the head-mounted frame. The photosensitive element is adapted to obtain first image data of a first target and body image data of a second target. The processor is electrically coupled to the photosensitive element and the projector. The memory storing color data, a first program, and a feature enhancement program, wherein the first program generates third image data according to the first image data and the color data for the projector to generate a third image on a reflective surface of the optical element. The feature enhancement program according to the body image data and the third image data for the projector to generate a fourth image on the reflective surface.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 14, 2019
    Applicant: Young Optics Inc.
    Inventors: Chih-Shan Tsai, Ching-Chao Tsai
  • Patent number: 10276375
    Abstract: A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Wen-Chen Lu, Chaos Tsai, Feng-Jia Shiu
  • Publication number: 20180144936
    Abstract: A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Hung-Wen Cho, Wen-Chen Lu, Chaos Tsai, Feng-Jia Shiu
  • Patent number: 9143754
    Abstract: Various embodiments are disclosed for modifying stereoscopic images. One embodiment is a method implemented in an image processing device for modifying stereoscopic images. The method comprises retrieving, by an image processing device, a stereoscopic image having at least a first view image and a second view image and retrieving an orientation selection relating to the stereoscopic image, the orientation selection comprising a selection other than one of: a horizontal flip selection and a 180 degree rotation selection. The method further comprises calculating a depth map according to at least part of the stereoscopic image, rotating the first view image based on the orientation selection to obtain a rotated first view image, and generating a new second view image according to the depth map and the rotated first view image.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 22, 2015
    Assignee: CYBERLINK CORP.
    Inventors: Yi-Chao Tsai, Chih-Yu Cheng
  • Patent number: 8868389
    Abstract: A computer-implemented simulation method for use in molding process by a computer processor includes specifying a simulating domain having a mold cavity configured to connect a tube of a molding machine, creating a mesh by dividing at least part of the simulating domain, generating at least one flow parameter of a molding material in the tube, specifying boundary conditions of the mesh by taking into consideration the at least one flow parameter of the molding material, and simulating a molding process of the molding material that is injected into the mold cavity by using the boundary conditions to generate a plurality of molding conditions.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 21, 2014
    Assignee: Coretech System Co., Ltd.
    Inventors: Rong Yeu Chang, Chia Hsiang Hsu, Chuan Wei Chang, Hsien Sen Chiu, Chao Tsai Huang
  • Publication number: 20140200710
    Abstract: A computer-implemented simulation method for use in molding process by a computer processor includes specifying a simulating domain having a mold cavity configured to connect a tube of a molding machine, creating a mesh by dividing at least part of the simulating domain, generating at least one flow parameter of a molding material in the tube, specifying boundary conditions of the mesh by taking into consideration the at least one flow parameter of the molding material, and simulating a molding process of the molding material that is injected into the mold cavity by using the boundary conditions to generate a plurality of molding conditions.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Applicant: CORETECH SYSTEM CO., LTD.
    Inventors: Rong Yeu CHANG, Chia Hsiang HSU, Chuan Wei CHANG, Hsien Sen CHIU, Chao Tsai HUANG
  • Patent number: 8671570
    Abstract: The vapor chamber is used in an electronic device. The electronic device includes a metal casing. The vapor chamber includes an upper cover, a working fluid, a waterproof layer, and a wick structure layer. The upper cover is disposed on inner walls of the metal casing to define a containing space. The working fluid is filled into the containing space. The waterproof layer is formed on inner walls of the containing space. The wick structure layer is formed on the waterproof layer.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 18, 2014
    Assignee: Pegatron Corporation
    Inventors: Juei-Khai Liu, Chao-Tsai Chung
  • Publication number: 20130202221
    Abstract: Various embodiments are disclosed for modifying stereoscopic images. One embodiment is a method implemented in an image processing device for modifying stereoscopic images. The method comprises retrieving, by an image processing device, a stereoscopic image having at least a first view image and a second view image and retrieving an orientation selection relating to the stereoscopic image, the orientation selection comprising a selection other than one of: a horizontal flip selection and a 180 degree rotation selection. The method further comprises calculating a depth map according to at least part of the stereoscopic image, rotating the first view image based on the orientation selection to obtain a rotated first view image, and generating a new second view image according to the depth map and the rotated first view image.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: CYBERLINK CORP.
    Inventors: Yi-Chao Tsai, Chih-Yu Cheng
  • Patent number: 8356656
    Abstract: A heat dissipation device and a heat dissipation method are provided. The device is disposed in a case having a first opening and a fan for generating a first cooling air flow. The device includes a heat dissipation element and an air-guiding plate. The heat dissipation element has a first region and a second region, and the first cooling air flow flows from the first region towards the second region. The air-guiding plate is disposed in the first region of the heat dissipation element and used for reducing a cross-sectional area of the first cooling air flow flowing in the first region along a flow direction of the first cooling air flow, so as to draw air outside the case into the second region via the first opening to generate a second cooling air flow, thereby lowering a temperature of the case located below the heat dissipation element.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 22, 2013
    Assignee: Pegatron Corporation
    Inventors: Yu-Wei Chang, Hu-Sung Chang, Chao-Tsai Chung
  • Publication number: 20120211203
    Abstract: A heat dissipating apparatus and a method for improving the same are provided. The heat dissipating apparatus includes a heat pipe including a heat-insulating section, a heat-absorbing part, and a heat-dissipating part. The heat-absorbing part is connected with one end of the heat-insulating section. The heat-absorbing part for contacting a heat source is thinner than the heat-insulating section. The heat-dissipating part is connected with the other end of the heat-insulating section.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 23, 2012
    Applicant: PEGATRON CORPORATION
    Inventors: Yu-Wei Chang, Chao-Tsai Chung