Patents by Inventor Chao Tsai

Chao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973163
    Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 30, 2024
    Assignee: Tianjin Sanan Optoelectronics Co., Ltd.
    Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng Liu, Weihuan Li, Liming Shu, Chao Liu
  • Publication number: 20240130242
    Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Ailian Zhao, Wu-Chang Tsai, Ashim Dutta, Chih-Chao Yang
  • Publication number: 20240108820
    Abstract: An atomization device and a method of predicting atomization time for the same are provided. The atomization device includes a control module, an atomization module and a breathing sensing module. The method includes: configuring the breath sensing module to detect inhalations of a user using the atomization device, so as to generate initial breath data correspondingly; and configuring the control module to perform: comparing inhalation data of the initial breath data with a valid inhalation standard to obtain valid inhalation data and filter noise; statistically analyzing the valid inhalation data to generate a predicted value of inhalation time; calculating an atomization time according to the predicted value of the inhalation time; and generating a driving signal to drive the atomization module to perform atomization according to the atomization time.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Inventors: CHIEN-SHEN TSAI, SHIH-CHAO LUO, YUAN-MING HSU, CHUN-CHIA JUAN
  • Patent number: 11950424
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
  • Publication number: 20240099035
    Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Wu-Chang Tsai, Ailian Zhao, Ashim Dutta, Chih-Chao Yang
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20230039611
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Yi-Fam SHIU, Cheng-Chao TSAI, Cheng-Lung WU, Chih-Hung HUANG, Jiun-Rong PAI
  • Publication number: 20210298203
    Abstract: An automotive electronic device durable in an automotive environment of at least 95° C. includes a bottom cover, a circuit board and a heatsink casing. The circuit board is installed on the bottom cover. The heatsink casing is assembled with the bottom cover, and covers the circuit board between the heatsink casing and the bottom cover. The heatsink casing includes an outer surface, a plurality of long fins and a plurality of side fins. The long fins are arranged on the outer surface along a first direction. Two adjacent ones of the long fins have a distance at least greater than 8 mm. The side fins are arranged on an edge of the outer surface along a second direction, and connected to one of the long fins.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 23, 2021
    Inventors: CHAO-TSAI CHUNG, PO-LIN LIN, SHU-TING CHAN
  • Publication number: 20190347833
    Abstract: A head-mounted electronic device including a head-mounted frame, a lens, a photosensitive element, a projector, an optical element, a processor, and a memory is provided. The lens and the projector are disposed on the head-mounted frame. The photosensitive element is adapted to obtain first image data of a first target and body image data of a second target. The processor is electrically coupled to the photosensitive element and the projector. The memory storing color data, a first program, and a feature enhancement program, wherein the first program generates third image data according to the first image data and the color data for the projector to generate a third image on a reflective surface of the optical element. The feature enhancement program according to the body image data and the third image data for the projector to generate a fourth image on the reflective surface.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 14, 2019
    Applicant: Young Optics Inc.
    Inventors: Chih-Shan Tsai, Ching-Chao Tsai
  • Patent number: 10276375
    Abstract: A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Wen-Chen Lu, Chaos Tsai, Feng-Jia Shiu
  • Publication number: 20180144936
    Abstract: A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Hung-Wen Cho, Wen-Chen Lu, Chaos Tsai, Feng-Jia Shiu
  • Patent number: 9143754
    Abstract: Various embodiments are disclosed for modifying stereoscopic images. One embodiment is a method implemented in an image processing device for modifying stereoscopic images. The method comprises retrieving, by an image processing device, a stereoscopic image having at least a first view image and a second view image and retrieving an orientation selection relating to the stereoscopic image, the orientation selection comprising a selection other than one of: a horizontal flip selection and a 180 degree rotation selection. The method further comprises calculating a depth map according to at least part of the stereoscopic image, rotating the first view image based on the orientation selection to obtain a rotated first view image, and generating a new second view image according to the depth map and the rotated first view image.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 22, 2015
    Assignee: CYBERLINK CORP.
    Inventors: Yi-Chao Tsai, Chih-Yu Cheng
  • Patent number: 8868389
    Abstract: A computer-implemented simulation method for use in molding process by a computer processor includes specifying a simulating domain having a mold cavity configured to connect a tube of a molding machine, creating a mesh by dividing at least part of the simulating domain, generating at least one flow parameter of a molding material in the tube, specifying boundary conditions of the mesh by taking into consideration the at least one flow parameter of the molding material, and simulating a molding process of the molding material that is injected into the mold cavity by using the boundary conditions to generate a plurality of molding conditions.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 21, 2014
    Assignee: Coretech System Co., Ltd.
    Inventors: Rong Yeu Chang, Chia Hsiang Hsu, Chuan Wei Chang, Hsien Sen Chiu, Chao Tsai Huang
  • Publication number: 20140200710
    Abstract: A computer-implemented simulation method for use in molding process by a computer processor includes specifying a simulating domain having a mold cavity configured to connect a tube of a molding machine, creating a mesh by dividing at least part of the simulating domain, generating at least one flow parameter of a molding material in the tube, specifying boundary conditions of the mesh by taking into consideration the at least one flow parameter of the molding material, and simulating a molding process of the molding material that is injected into the mold cavity by using the boundary conditions to generate a plurality of molding conditions.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Applicant: CORETECH SYSTEM CO., LTD.
    Inventors: Rong Yeu CHANG, Chia Hsiang HSU, Chuan Wei CHANG, Hsien Sen CHIU, Chao Tsai HUANG
  • Patent number: 8671570
    Abstract: The vapor chamber is used in an electronic device. The electronic device includes a metal casing. The vapor chamber includes an upper cover, a working fluid, a waterproof layer, and a wick structure layer. The upper cover is disposed on inner walls of the metal casing to define a containing space. The working fluid is filled into the containing space. The waterproof layer is formed on inner walls of the containing space. The wick structure layer is formed on the waterproof layer.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 18, 2014
    Assignee: Pegatron Corporation
    Inventors: Juei-Khai Liu, Chao-Tsai Chung
  • Publication number: 20130202221
    Abstract: Various embodiments are disclosed for modifying stereoscopic images. One embodiment is a method implemented in an image processing device for modifying stereoscopic images. The method comprises retrieving, by an image processing device, a stereoscopic image having at least a first view image and a second view image and retrieving an orientation selection relating to the stereoscopic image, the orientation selection comprising a selection other than one of: a horizontal flip selection and a 180 degree rotation selection. The method further comprises calculating a depth map according to at least part of the stereoscopic image, rotating the first view image based on the orientation selection to obtain a rotated first view image, and generating a new second view image according to the depth map and the rotated first view image.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: CYBERLINK CORP.
    Inventors: Yi-Chao Tsai, Chih-Yu Cheng
  • Patent number: 8356656
    Abstract: A heat dissipation device and a heat dissipation method are provided. The device is disposed in a case having a first opening and a fan for generating a first cooling air flow. The device includes a heat dissipation element and an air-guiding plate. The heat dissipation element has a first region and a second region, and the first cooling air flow flows from the first region towards the second region. The air-guiding plate is disposed in the first region of the heat dissipation element and used for reducing a cross-sectional area of the first cooling air flow flowing in the first region along a flow direction of the first cooling air flow, so as to draw air outside the case into the second region via the first opening to generate a second cooling air flow, thereby lowering a temperature of the case located below the heat dissipation element.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 22, 2013
    Assignee: Pegatron Corporation
    Inventors: Yu-Wei Chang, Hu-Sung Chang, Chao-Tsai Chung
  • Publication number: 20120211203
    Abstract: A heat dissipating apparatus and a method for improving the same are provided. The heat dissipating apparatus includes a heat pipe including a heat-insulating section, a heat-absorbing part, and a heat-dissipating part. The heat-absorbing part is connected with one end of the heat-insulating section. The heat-absorbing part for contacting a heat source is thinner than the heat-insulating section. The heat-dissipating part is connected with the other end of the heat-insulating section.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 23, 2012
    Applicant: PEGATRON CORPORATION
    Inventors: Yu-Wei Chang, Chao-Tsai Chung
  • Publication number: 20120214081
    Abstract: Disclosed is a laminate for use in a fuel cell. The laminate includes at least two field plates and a bonding layer. Each of the flow field plates includes a plate and channels defined therein. The bonding layer is made in the form of an annular strip and sandwiched between the flow field plates, around the channels.
    Type: Application
    Filed: February 21, 2011
    Publication date: August 23, 2012
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Chien-Kuo Liu, Kin-Fu Lin, Kun-Chao Tsai