Patents by Inventor Chao-Tsung Tseng

Chao-Tsung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230154861
    Abstract: A semiconductor packaging substrate is provided, which includes a build-up circuit structure, at least one fiducial marker structure, and an insulating protective layer. The fiducial marker structure includes a fiducial marker and a second insulating layer covering the fiducial marker. The second insulating layer is made of a transparent insulation material, so that the fiducial marker inside the second insulating layer can be seen through a CCD lens or tool maker microscope for alignment so as to easily create a smaller see-through area and the process parameters can be easily controlled. Besides, the disclosure further provides a manufacturing method for the semiconductor packaging substrate.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 18, 2023
    Inventors: CHAO-TSUNG TSENG, CHE-WEI HSU
  • Patent number: 11552014
    Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 10, 2023
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chao-Tsung Tseng
  • Publication number: 20220238425
    Abstract: A semiconductor package structure includes a chip, a first conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with a first metal electrode pad and a second side with a second metal electrode pad. The first conductive pillar is disposed adjacent to the chip. The dielectric layer covers the chip and the first conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the first conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the first conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric.
    Type: Application
    Filed: April 13, 2022
    Publication date: July 28, 2022
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chao-Tsung Tseng
  • Publication number: 20210159151
    Abstract: A sensing device includes a sensing chip, which has an active face with a sensing region and a metal pad region having at least a metal pad thereon; a dielectric layer, which covers a periphery, back surface and a part of the active surface of the sensing chip, and the first face of the dielectric layer has an elevation higher than the active face of the sensing chip and exposes the sensing region of the sensing chip; a first conductive wire layer and a second conductive wire layer, which are disposed on the first and second faces of the dielectric layer respectively; a conductive pillar, which is disposed within the dielectric layer and connected to the first and second conductive wire layers; and a front-face fan-out circuit, which is connected to the first conductive wire layer and the metal pad of the sensing chip.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 27, 2021
    Inventors: Chao-Tsung Tseng, Che-Wei Hsu
  • Publication number: 20200161234
    Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 21, 2020
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chao-Tsung Tseng
  • Publication number: 20180261578
    Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping HSU, Chao-Tsung TSENG
  • Patent number: 9806012
    Abstract: The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a dielectric layer and a patterned conductor layer. The dielectric layer has at least one opening groove. The patterned conductor layer is embedded in the dielectric layer, wherein a part of the patterned conductor layer is as a conductive pillar, which has two exposed ends, and a part of the patterned conductor layer is as a conductive wire, which only has one exposed end.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 31, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Chao-Tsung Tseng
  • Publication number: 20170162492
    Abstract: The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a dielectric layer and a patterned conductor layer. The dielectric layer has at least one opening groove. The patterned conductor layer is embedded in the dielectric layer, wherein a part of the patterned conductor layer is as a conductive pillar, which has two exposed ends, and a part of the patterned conductor layer is as a conductive wire, which only has one exposed end.
    Type: Application
    Filed: July 11, 2016
    Publication date: June 8, 2017
    Inventors: Shih-Ping Hsu, Chao-Tsung Tseng
  • Patent number: 9583436
    Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: February 28, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chao-Tsung Tseng, Shih-Ping Hsu, Chin-Ming Liu, Che-Wei Hsu
  • Publication number: 20160190059
    Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.
    Type: Application
    Filed: May 29, 2015
    Publication date: June 30, 2016
    Inventors: CHAO-TSUNG TSENG, Shih-Ping Hsu, Chin-Ming Liu, Che-Wei Hsu
  • Publication number: 20060112352
    Abstract: The present invention relates to a video program menu system and menu control device thereof. The main structure comprises a video converting device, a display screen, and a menu control device. The video converting device can be used to receive at least one video on demand program data and comprises a plurality of program class name fields, a plurality of program data display sections, and a program preview section therein. A main menu and a sub-menu can be arranged on the display screen. At least one program class name fields will be displayed on the main menu, and a plurality of program data display sections and a program preview display section are displayed on the sub-menu. The program data display section is used to show a name or description of one of the programs. When a consumer chooses to highlight one of the program data display sections, program preview content of the highlighted program data display section can be displayed in the program preview display section.
    Type: Application
    Filed: January 4, 2005
    Publication date: May 25, 2006
    Inventors: Chao-Tsung Tseng, Yao Hsu