Patents by Inventor Chao-Tzung Tsai
Chao-Tzung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11183405Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.Type: GrantFiled: April 19, 2019Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Tzung Tsai, Tzu Ken Lin, I-Chang Wu, Ching-Lun Lai, Li-Jia Liou
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Publication number: 20190244841Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.Type: ApplicationFiled: April 19, 2019Publication date: August 8, 2019Inventors: CHAO-TZUNG TSAI, TZU KEN LIN, I-CHANG WU, CHING-LUN LAI, LI-JIA LIOU
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Patent number: 10269599Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.Type: GrantFiled: June 20, 2014Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Tzung Tsai, Tzu Ken Lin, I-Chang Wu, Ching-Lun Lai, Li-Jia Liou
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Publication number: 20160035563Abstract: An apparatus for processing a semiconductor wafer includes a factory interface configured to couple with a manufacturing chamber. The factory interface includes a robot; an orienter adjacent to the robot; and a particle remover above the orienter and facing toward a wafer. The particle remover is configured to blow ionized gas on a surface of the wafer so as to remove particles.Type: ApplicationFiled: August 1, 2014Publication date: February 4, 2016Inventors: TZU-KEN LIN, YUNG CHING CHEN, I-CHANG WU, CHAO-TZUNG TSAI, CHING-LUN LAI
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Publication number: 20150371882Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: CHAO-TZUNG TSAI, TZU KEN LIN, I-CHANG WU, CHING-LUN LAI, LI-JIA LIOU
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Patent number: 7339253Abstract: Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such that the trench is sealed and a space is formed within the layer of silicon oxide. The space can contain a vacuum or any of a variety of gases depending upon conditions of the thermal oxidation step. Retrograde trench isolation structures containing a space are also provided.Type: GrantFiled: August 16, 2004Date of Patent: March 4, 2008Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Tzung Tsai, Ling-Sung Wang, Ching Lang Yen
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Patent number: 7301645Abstract: A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.Type: GrantFiled: February 7, 2005Date of Patent: November 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shiang-Bau Wang, Yuan-Hung Chiu, Hun-Jan Tao, Chao-Tzung Tsai
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Publication number: 20060046323Abstract: A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.Type: ApplicationFiled: February 7, 2005Publication date: March 2, 2006Inventors: Shiang-Bau Wang, Yuan-Hung Chiu, Hun-Jan Tao, Chao-Tzung Tsai
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Publication number: 20060033179Abstract: Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such that the trench is sealed and a space is formed within the layer of silicon oxide. The space can contain a vacuum or any of a variety of gases depending upon conditions of the thermal oxidation step. Retrograde trench isolation structures containing a space are also provided.Type: ApplicationFiled: August 16, 2004Publication date: February 16, 2006Inventors: Chao-Tzung Tsai, Ling-Sung Wang, Ching Yen
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Patent number: 6962878Abstract: A method for reducing the dimension of a patterned organic photoresist area by reducing the pressure of a reactive environment surrounding the patterned photoresist to cause outgasing. The outgased materials CxHyOz are then decomposed in the reactive environment leaving the outgased photoresist porous. The environment surrounding the patterned photoresist is then increased to atmospheric pressure, which compresses or shrinks the porous photoresist. Photoresist lines having a dimension as small as about 0.085 ?m can be obtained.Type: GrantFiled: April 17, 2003Date of Patent: November 8, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Chen Su, Chao-Tzung Tsai
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Patent number: 6878646Abstract: A method of reducing the critical dimension (CD) of a hard mask by a wet etch method is described. An oxide hard mask is treated with a H2SO4/H2O2 (SPM) solution followed by treatment with a NH4OH/H2O2/H2O (APM) solution to trim the CD by 0 to 20 nm. With nitride or oxynitride hard masks, a buffered HF dip is inserted prior to the SPM treatment. For oxide hard masks, the SPM solution performs the etch while APM solution assists in removing plasma etch residues. With oxynitride hard masks, the APM performs the etch while BHF and SPM solutions remove plasma etch residues. The hard mask pattern can then be transferred with a dry etch into an underlying polysilicon layer to form a gate length of less than 150 nm while controlling the CD to within 3 to 5 nm of a targeted value.Type: GrantFiled: October 16, 2002Date of Patent: April 12, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Tzung Tsai, Jia-Sheng Wu, Fuxuan Fang
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Publication number: 20040209480Abstract: A method for reducing the dimension of a patterned organic photoresist area by reducing the pressure of a reactive environment surrounding the patterned photoresist to cause outgasing. The outgased materials CxHyOz are then decomposed in the reactive environment leaving the outgased photoresist porous. The environment surrounding the patterned photoresist is then increased to atmospheric pressure, which compresses or shrinks the porous photoresist. Photoresist lines having a dimension as small as about 0.085 &mgr;m can be obtained.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Inventors: Yih-Chen Su, Chao-Tzung Tsai