Patents by Inventor Chao-Wei HSU

Chao-Wei HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081531
    Abstract: The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-Wei HSU
  • Patent number: 12183797
    Abstract: The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-Wei Hsu
  • Publication number: 20240387703
    Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes depositing a top epitaxial layer over a substrate, forming a fin structure from the top epitaxial layer and a portion of the substrate, recessing a source/drain region of the fin structure to form a source/drain recess, conformally depositing a semiconductor layer over surfaces of the source/drain recess, etching back the semiconductor layer to form a diffusion stop layer over a bottom surface of the source/drain recess, depositing a first epitaxial layer over the diffusion stop layer and sidewalls source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, and depositing a third epitaxial layer over the second epitaxial layer. A germanium concentration of the diffusion stop layer is greater than a germanium concentration of the top epitaxial layer or a germanium concentration of the first epitaxial layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventor: Chao-Wei Hsu
  • Publication number: 20230120656
    Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes depositing a top epitaxial layer over a substrate, forming a fin structure from the top epitaxial layer and a portion of the substrate, recessing a source/drain region of the fin structure to form a source/drain recess, conformally depositing a semiconductor layer over surfaces of the source/drain recess, etching back the semiconductor layer to form a diffusion stop layer over a bottom surface of the source/drain recess, depositing a first epitaxial layer over the diffusion stop layer and sidewalls source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, and depositing a third epitaxial layer over the second epitaxial layer. A germanium concentration of the diffusion stop layer is greater than a germanium concentration of the top epitaxial layer or a germanium concentration of the first epitaxial layer.
    Type: Application
    Filed: March 29, 2022
    Publication date: April 20, 2023
    Inventor: Chao-Wei Hsu
  • Publication number: 20220367657
    Abstract: The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.
    Type: Application
    Filed: September 10, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chao-Wei HSU
  • Patent number: 11309419
    Abstract: A semiconductor device includes a semiconductor fin and a gate structure above the semiconductor fin. The semiconductor fin includes a bottom portion and a top portion above the bottom portion. The bottom portion and the top portion are made of different materials. The top portion includes a head part and a neck part between the head part and the bottom portion. The neck part has a width less than a width of the head part, and the neck part is in contact with the bottom portion.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Patent number: 11177358
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Publication number: 20210226051
    Abstract: A semiconductor device includes a semiconductor fin and a gate structure above the semiconductor fin. The semiconductor fin includes a bottom portion and a top portion above the bottom portion. The bottom portion and the top portion are made of different materials. The top portion includes a head part and a neck part between the head part and the bottom portion. The neck part has a width less than a width of the head part, and the neck part is in contact with the bottom portion.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei HSU
  • Publication number: 20200273957
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventor: Chao-Wei HSU
  • Patent number: 10680075
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Publication number: 20200105888
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction
    Type: Application
    Filed: May 30, 2019
    Publication date: April 2, 2020
    Inventor: Chao-Wei HSU