Patents by Inventor Chao-Wei Lin

Chao-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271207
    Abstract: A method for controlling a plurality of autonomous robots for performing environment maintenance operations includes: generating a setup command that indicates a selected location, a plurality of selected robots, an available time slot, and a distribution mode signal that indicates whether the selected robots are to be controlled based on the available time slot or an inputted priority section; and generating a plurality of sub-routes based on different parameters, depending on the distribution mode signal. The sub-routes are generated to be connected into an unbroken trail. Then, the sub-routes are transmitted to the selected robots, respectively, so as to control each of the selected robots to move along the respective one of the sub-routes.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: April 8, 2025
    Assignee: URSrobot AI Inc.
    Inventors: Chien-Tung Chen, Chung-Hou Wu, Chao-Cheng Chen, Wen-Wei Chiang, Yi-Jin Lin
  • Publication number: 20250110307
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20250109763
    Abstract: A fastener includes a screw head and a screw shank. The screw head has four driven wall portions and four guiding wall portions that are disposed about a central axis of the fastener in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. The driven wall portions and the guiding wall portions cooperatively define a driven recess that has an opening. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections.
    Type: Application
    Filed: February 14, 2024
    Publication date: April 3, 2025
    Inventor: Chao-Wei LIN
  • Publication number: 20250109764
    Abstract: A fastener includes a screw head that includes a driven protrusion having four driven wall portions and four guiding wall portions which are disposed about a central axis of the fastener in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight, and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections. A central angle of the curved section of each of the driven wall portions is smaller than 180 degrees.
    Type: Application
    Filed: February 14, 2024
    Publication date: April 3, 2025
    Inventor: Chao-Wei LIN
  • Publication number: 20250109765
    Abstract: A nut includes a nut body that defines a circular hole, and that has four driven wall portions and four guiding wall portions disposed about a central axis of the nut in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight, and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections. A central angle of the curved section of each of the driven wall portions is smaller than 180 degrees.
    Type: Application
    Filed: February 14, 2024
    Publication date: April 3, 2025
    Inventor: Chao-Wei LIN
  • Patent number: 12266559
    Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng
  • Publication number: 20250093593
    Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.
    Type: Application
    Filed: January 3, 2024
    Publication date: March 20, 2025
    Inventors: Wen-Chih Lin, Cheng-Yu Kuo, Yen-Hung Chen, Hsuan-Ting Kuo, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou, Ming-Fa Chen, Shang-Yun Hou
  • Publication number: 20250076594
    Abstract: Optical devices and methods of manufacture are presented in which a multi-tier connector is utilized to transmit and receive optical signals to and from an optical device. In embodiments a multi-tier connection unit receives optical signals from outside of an optical device, wherein the optical signals are originally in multiple levels. The multi-tier connection unit then routes the optical signals into a single level of optical components.
    Type: Application
    Filed: December 18, 2023
    Publication date: March 6, 2025
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Yi-Jan Lin, Yu-Sheng Huang, Tsung-Fu Tsai, Chao-Jen Wang, Szu-Wei Lu
  • Patent number: 12243924
    Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Patent number: 12237369
    Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: February 25, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
  • Publication number: 20250062181
    Abstract: A method includes depositing a first metal layer on a package component, wherein the package component comprises a first device die, forming a dielectric layer on the package component, and plating a metal thermal interface material on the first metal layer. The dielectric layer includes portions on opposing sides of the metal thermal interface material. A heat sink is bonded on the metal thermal interface material. The heat sink includes a second metal layer physically joined to the metal thermal interface material.
    Type: Application
    Filed: November 13, 2023
    Publication date: February 20, 2025
    Inventors: Chao-Wei Chiu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 12228980
    Abstract: A mounting system for an electronic device is disclosed. The mounting system includes a mounting plate; a plurality of fasteners for coupling the mounting plate with the electronic device; a single main gear mounted on the mounting plate; a plurality of secondary gears coupled, respectively, to the plurality of fasteners; and a plurality of intermediate gears mounted on the mounting plate and rotationally coupled between the single main gear and the plurality of secondary gears. Rotation of each of the plurality of secondary gears causes a fastening movement of a respective one of the plurality of fasteners. Simultaneous rotation of the plurality of intermediate gears causes the plurality of secondary gears to rotate simultaneously in response to a single rotational force being received by the main gear. The simultaneous rotation of the plurality of intermediate gears causes a simultaneous fastening movement of the plurality of secondary gears.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: February 18, 2025
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Wei Lin, Yu-Nien Huang, Ming-Lun Liu
  • Publication number: 20250054892
    Abstract: A package structure including a first substrate and a second substrate is provided. The first substrate includes first bumps with first lateral dimension and second bumps with second lateral dimension. The first bumps are distributed in a first region of the first substrate, and the second bumps are distributed in the second region of the first substrate, wherein the first lateral dimension is greater than the second lateral dimension, and a first bump height of the first bumps is smaller than a second bump height of the second bumps. The second substrate includes conductive terminals electrically connected to the first bumps and the second bumps.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Chiu, Wei-Yu Chen, Hsin Liang Chen, Hao-Jan Shih, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 12224210
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Publication number: 20250042757
    Abstract: Hydrofluoric acid waste streams from semiconductor device manufacturing processes are collected and converted to cryolite utilizing disclosed systems and processes. The systems and processes are able to utilize hydrofluoric acid waste streams from multiple different sources. The systems and processes utilizing control delivery of reactant so that the produced cyrolite has low impurity levels and meets industry standards.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 6, 2025
    Inventors: You-Shiun LIN, Chao-Chun CHANG, Kuo-Wei CHEN, Yi-Chen LI, Tsung Lung LU
  • Patent number: 12218082
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12219747
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240412772
    Abstract: A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.
    Type: Application
    Filed: October 4, 2023
    Publication date: December 12, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yifei Yan, Hui-Huang Chen, Chao-Wei Lin
  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen