Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A fastener includes a screw head and a screw shank. The screw head has a top surface and an inner surrounding surface. The inner surrounding surface has six curved portions and six driven portions disposed in an alternating arrangement. Each of the driven portions has a curved section connected to one of two adjacent curved portions and having a direction of curvature opposite to that of the one of the two adjacent curved portions, a straight section extending along a tangent line of an end of the curved section, and an extension section connected between the straight section and the other one of the two adjacent curved portions.

Abstract: A fastener includes a screw head that includes a driven protrusion having four driven wall portions and four guiding wall portions which are disposed about a central axis of the fastener in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight, and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections. A central angle of the curved section of each of the driven wall portions is smaller than 180 degrees.

Abstract: A nut includes a nut body that defines a circular hole, and that has four driven wall portions and four guiding wall portions disposed about a central axis of the nut in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight, and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections. A central angle of the curved section of each of the driven wall portions is smaller than 180 degrees.

Abstract: A fastener includes a screw head and a screw shank. The screw head has four driven wall portions and four guiding wall portions that are disposed about a central axis of the fastener in an alternating arrangement. The driven wall portions are equiangularly spaced apart from each other. Each of the guiding wall portions is straight and has two opposite ends that are respectively connected to two of the driven wall portions adjacent to the guiding wall portion. The driven wall portions and the guiding wall portions cooperatively define a driven recess that has an opening. A ratio of a longest distance between two of the driven wall portions that are non-adjacent to each other to a longest distance between two of the driven wall portions that are adjacent to each other is greater than 1.16. Each of the driven wall portions has a curved section and two straight sections.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.

Abstract: The present disclosure provides a recyclable golf shoe. The shoe may comprise an upper and a sole assembly. The upper may comprise: a membrane layer configured to at least partially surround or enclose a foot of a subject wearing the golf shoe; an internal A-shaped frame structure attached or coupled to the membrane layer to structurally support or stiffen the upper; a mesh layer comprising a first side and a second side, the first side attached or coupled to the membrane layer and the internal A-shaped frame structure; and a saddle connected to the second side of the mesh layer. The membrane layer, the internal A-shaped frame structure, the mesh layer, and the saddle may comprise one or more recyclable thermoplastic urethane (TPU) materials that can be processable into another article or component comprising at least one recycled or recyclable TPU material.

Abstract: The present disclosure provides a recyclable golf shoe. The golf shoe may comprise an upper comprising a mesh layer and a sole assembly connected to the upper. The sole assembly comprises a first plurality of foam layers in a rearfoot region of the golf shoe, a second plurality of foam layers extending between the rearfoot region of the golf shoe and a forefoot region of the golf shoe, and a support positioned adjacent to the second plurality of foam layers. The second plurality of foam layers is positioned between the first plurality of foam layers and the support. The mesh layer, the first and/or second plurality of foam layers, and the support may comprise one or more recyclable polyethylene terephthalate (PET) materials.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.

Abstract: A wood screw includes a head, a shank axially extending from the head, a main thread extending helically around the shank in a tightening direction and having an outer diameter ranging from 3 to 16 mm, and a plurality of forward ribs extending spirally around the shank in a same direction as the main thread. The number of the forward ribs ranges from three to five. Each forward rib, in a cross section thereof, has a first outer edge facing the tightening direction, and a second outer edge facing opposite the tightening direction and having a length shorter than that of the first outer edge. Each forward rib has a height smaller than that of the main thread, and a lead angle greater than that of the main thread.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

Abstract: A fastener includes a screw head and a screw shank. The screw head has a top surface and an inner surrounding surface. The inner surrounding surface has six curved portions and six driven portions disposed in an alternating arrangement. Each of the driven portions has a curved section connected to one of two adjacent curved portions and having a direction of curvature opposite to that of the one of the two adjacent curved portions, a straight section extending along a tangent line of an end of the curved section, and an extension section connected between the straight section and the other one of the two adjacent curved portions.

Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.