Abstract: An emulated current generation circuit of a power converting circuit, providing an emulated current includes an AC component current and a DC component current, includes a first current circuit, a second current circuit, a combination circuit and a calibration circuit. The first current circuit generates a ramp signal as the AC component current. The second current circuit is coupled to an output stage of power converting circuit to provide a sensing current. The DC component current is generated after performing a sample-and-hold processing on the sensing current. The combination circuit is coupled to the first current circuit and second current circuit respectively to combine the AC component current and DC component current into an emulated sensing current. The calibration circuit is coupled to the first current circuit, second current circuit and combination circuit to dynamically adjust the ramp signal according to the emulated sensing current and sensing current.

Abstract: An emulated current generation circuit of a power converting circuit, providing an emulated current includes an AC component current and a DC component current, includes a first current circuit, a second current circuit, a combination circuit and a calibration circuit. The first current circuit generates a ramp signal as the AC component current. The second current circuit is coupled to an output stage of power converting circuit to provide a sensing current. The DC component current is generated after performing a sample-and-hold processing on the sensing current. The combination circuit is coupled to the first current circuit and second current circuit respectively to combine the AC component current and DC component current into an emulated sensing current. The calibration circuit is coupled to the first current circuit, second current circuit and combination circuit to dynamically adjust the ramp signal according to the emulated sensing current and sensing current.

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.

Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

Abstract: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.

Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

Abstract: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

Abstract: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.