Patents by Inventor Chao-Wei Wu

Chao-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230190375
    Abstract: A verification block structure and a verification system for orthopedic surgery are provided. The verification block structure includes a base and an artificial bone block. The base has a carrying portion and a bottom corresponding to the carrying portion. The artificial bone block is detachably fixed to the carrying portion of the base, and a shape or a material of the artificial bone block is determined upon a bone characteristic of a patient and/or a surgical method.
    Type: Application
    Filed: March 24, 2022
    Publication date: June 22, 2023
    Inventors: MING-CHUN HO, CHIH-HSIANG HSIEH, CHAO-WEI WU, CHIA-HO YEN, WEN-TENG WANG, SHYUE-CHERNG JUANG
  • Publication number: 20230118765
    Abstract: A medical device is provided. The medical device includes a parallel manipulator. The parallel manipulator has an end platform coupled to a surgical tool and a base platform coupled to a machine module. The machine module is coupled to the surgical tool through a transmission shaft disposed between the end platform and the base platform. The transmission shaft has a transmission yoke, a runner, a first rod coupled to the transmission yoke, a second rod coupled to the runner, and a universal joint coupled between the first rod and the second rod.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KUN-PIN HUANG, CHIH-HSIANG HSIEH, CHAO-WEI WU, MING-CHUN HO
  • Patent number: 10636873
    Abstract: A method of fabricating a semiconductor device is provided. In the method, a gate structure is formed on a semiconductor substrate. A photolithography process is performed with a mask having two transparent regions to form a photoresist layer having two openings in the semiconductor substrate. A first photoresist layer of the photoresist layer between the two openings is aligned to the gate structure and formed on the gate structure. The width of the first photoresist layer is shorter than the width of the gate structure such that a first side portion and a second side portion of the gate structure are exposed from both sides of the first photoresist layer, respectively. Next, an ion implantation process is performed to form lightly doped drain regions in the semiconductor substrate which are on two opposite sides of the gate structure of the photoresist layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 28, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Wei Lin, Tsung-Han Lin, Chao-Wei Wu, Yen-Kai Chen
  • Publication number: 20190157392
    Abstract: A method of fabricating a semiconductor device is provided. In the method, a gate structure is formed on a semiconductor substrate. A photolithography process is performed with a mask having two transparent regions to form a photoresist layer having two openings in the semiconductor substrate. A first photoresist layer of the photoresist layer between the two openings is aligned to the gate structure and formed on the gate structure. The width of the first photoresist layer is shorter than the width of the gate structure such that a first side portion and a second side portion of the gate structure are exposed from both sides of the first photoresist layer, respectively. Next, an ion implantation process is performed to form lightly doped drain regions in the semiconductor substrate which are on two opposite sides of the gate structure of the photoresist layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Wei LIN, Tsung-Han LIN, Chao-Wei WU, Yen-Kai CHEN
  • Patent number: 9660073
    Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 23, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Wei Lin, Pi-Kuang Chuang, Chao-Wei Wu