Patents by Inventor Chao-Wen Cheng

Chao-Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071362
    Abstract: In example implementations, a computing device is provided. The computing device includes a system management bus, a controller communicatively coupled to the system management bus, a noise generating component communicatively coupled to the controller, a noise cancellation codec communicatively coupled to the system management bus, and a speaker communicatively coupled to the noise cancellation codec. The operating parameters of the noise generating component are provided to the controller. The noise cancellation codec is to receive the operating parameters of the noise generating component from the controller via the system management bus and to generate a noise cancellation signal based on the operating parameters. The speaker outputs the noise cancellation signal to cancel noise generated by the noise generating component.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Chao-Wen Cheng, Tsung Yen Chen, Wen Shih Chen, Mo-Hsuan Lin, Juiching Chang
  • Patent number: 11877416
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a riser card body, a first interface, a first 2×8 slot on a surface of the riser card body, and a second 2×8 slot on a same side of the surface of the riser card body as the first 2×8 slot. The first interface includes a first set of fingers and a second set of fingers at an end of the riser card body to connect to a peripheral component interconnect express (PCIe) slot of a motherboard. The first 2×8 slot and the second 2×8 slot are positioned perpendicular to the PCIe slot of the motherboard.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 16, 2024
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yu Lih Chuang, Yen-Tang Chang, Heather Louise Burnam Volesky, Jonathan D. Bassett, Wen Bin Lin, Chao-Wen Cheng
  • Publication number: 20230400220
    Abstract: In some examples, an electronic device includes an audio output device, an airflow generator to generate an airflow, and a system controller to control an operational speed of the airflow generator. The electronic device further includes an audio controller to generate a noise cancellation audio output based on an indicator of the operational speed of the airflow generator provided from the system controller to the audio controller, and send the noise cancellation audio output to the audio output device to mitigate noise produced by the airflow generator.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Chao-Wen Cheng, Tsung-Yen Chen, Chien Fa Huang, Wen Shih Chen, Mo-Hsuan Lin
  • Publication number: 20230384843
    Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a memory, a controller, and a configuration change module. The expansion interface includes a plurality of slots to connect to a respective add-in card and a re-timer to control an operation of the plurality of slots. The memory is to store a firmware that sets a configuration of the plurality of slots, wherein the re-timer is to control the operation of the plurality of slots in accordance with the configuration set by the firmware. The controller is to control operation of the expansion interface. The configuration change module is to change the configuration of the plurality of slots when a change in a number of connected add-in cards is detected.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Jui Ching Chang, Chao-Wen Cheng, Tsung Yen Chen, Chien-Cheng Su
  • Patent number: 11824447
    Abstract: An example redundant power supply system comprises a power supply input to receive power from a power supply; a buck-boost converter coupled to the power supply input; and a controller coupled to the buck-boost converter. The controller is to receive a power supply identification signal from the power supply. The controller is also to enable or disable the buck-boost converter based on the power supply identification signal.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 21, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chao-Wen Cheng, Ying-Chi Chou, Feng Ming Lu, Chien Fa Huang, Chieh-Shen Huang, Tsung Yen Chen, Peter Seiler, Poying Chih
  • Publication number: 20230324978
    Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface that includes a plurality of slots. A first add-in card is connected to a first slot of the plurality of slots. A second add-in card is connected to a second slot of the plurality of slots. The computing device includes a processor communicatively coupled to the expansion interface. The processor is to detect that the first add-in card is compatible with a power savings control signal and that the second add-in card is not compatible with the power savings control signal, disable the power savings control signal to the second slot, and transmit the power savings control signal to the first slot when the first add-in card goes into a power savings mode.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Inventors: Jui Ching Chang, Chien-Cheng Su, Chao-Wen Cheng, Wen-Bin Lin
  • Publication number: 20230315667
    Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Wen Bin Lin, ChiWei Ding, Chun Yi Liu, Shuo-Cheng Cheng, Chao-Wen Cheng
  • Publication number: 20230289302
    Abstract: In example implementations, a computing device is provided. The computing device includes a memory bus, a first memory module connected to a first slot of the memory bus, a second memory module connected to a second slot of the memory bus, and a processor communicatively coupled to the memory bus. The processor is to detect a mixed memory module configuration caused by the first memory module and the second memory module and train the first memory module and the second memory module to operate at a maximum mixed memory module configuration speed.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Cheng-Yi Yang
  • Publication number: 20230251865
    Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, a previous generation carrier connected to the interface, a controller communicatively coupled to the interface, and a basic input/output system (BIOS). The previous generation carrier includes a current generation memory card. The controller is to detect the previous generation carrier. The BIOS is to set the interface to operate at a speed associated with the previous generation carrier in response to detection of the previous generation carrier.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 10, 2023
    Inventors: CHAO-WEN CHENG, WEN SHIH CHEN, CHEN-PANG CHANG, YI-FENG LIN
  • Publication number: 20230240036
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a riser card body, a first interface, a first 2×8 slot on a surface of the riser card body, and a second 2×8 slot on a same side of the surface of the riser card body as the first 2×8 slot. The first interface includes a first set of fingers and a second set of fingers at an end of the riser card body to connect to a peripheral component interconnect e×press (PC1e) slot of a motherboard. The first 2×8 slot and the second 2×8 slot are positioned perpendicular to the PCIe slot of the motherboard.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventors: Yu Lih Chuang, Yen-Tang Chang, Heather Louise Burnam Volesky, Jonathan D. Bassett, Wen Bin Lin, Chao-Wen Cheng
  • Publication number: 20230213915
    Abstract: Examples for controlling an operating speed of a cooling device based on an operating mode of a processing unit, are described. In an example, a current value of a monitored current signal is determined. Based on the comparison of the current value with a predefined threshold value, a switch in an operating mode of the processing unit is determined. Thereafter, the computing device may be caused to increase the operating speed of the cooling device to a designated speed.
    Type: Application
    Filed: June 19, 2020
    Publication date: July 6, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Yu-Fan Chen, Mo-Hsuan Lin
  • Patent number: 11644881
    Abstract: Techniques for reallocating power between a plurality of electronic components and a connection port of a computing system are described. In operation, operational state of an electronic component from amongst multiple electronic components is analysed. Based on the operational state of the electronic component, an unused power available with the electronic components is determined. Based on the availability of the unused power, a default power level associated with the connection port is increased, where the default power level is a predefined power allocated to the connection port for operation.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 9, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chao Wen Cheng, Po Ying Chih, Yen Tang Chang
  • Patent number: 11630500
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 18, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • Publication number: 20230028599
    Abstract: Structures and functions of power supplies are disclosed. In an example, a power supply includes a power factor correction circuit and a bypass circuit. The bypass circuit bypasses the power factor correction circuit when the switch of the bypass circuit is on in response to a predetermined range of input power of the power supply. The bypass circuit also includes a delay circuit to delay the activation of the bypass circuits in response to the predetermined range of input power of the power supply for a predetermined time period.
    Type: Application
    Filed: December 20, 2019
    Publication date: January 26, 2023
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Chao-Wen Cheng
  • Publication number: 20230028263
    Abstract: In an example, a card retainer may include a latch to removably engage with a free end of an expansion card. Further, a card retainer may include a pivot mount to attach the latch to a system board of a computing device. In some examples, the latch is movable about the pivot mount between an open position and a closed position. The latch may exert a bias force on the free end of the expansion card in order to retain the expansion card to the system board in a secure manner when the latch is disposed in the closed position.
    Type: Application
    Filed: January 10, 2020
    Publication date: January 26, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Xiang Ma, Chan Woo Park, Baosheng Zhang, Richard Lin, Fangyong Dai, Chao-Wen Cheng, Chien Fa Huang, Roger Allen Pearson
  • Patent number: 11537189
    Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 27, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Roger A. Pearson, Jonathan D. Bassett
  • Patent number: 11393554
    Abstract: In one example, a device housing is described, which may include a base substrate and ion-exchanged glass beads disposed on an outer surface of the base substrate.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 19, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Ya-Ting Yeh, Chao-Wen Cheng, Hsin-Yi Lee
  • Patent number: 11392530
    Abstract: In one example, an adapter card may include a circuit board having a male interface to be inserted into a discrete graphics card slot and a peripheral component interconnect express (PCIe) slot to communicatively couple a PCIe device. Further, the adapter card may include a voltage converter circuit disposed on the circuit board to convert a first voltage associated with the discrete graphics card slot to a second voltage corresponding to the PCIe device and a level shifter circuit disposed on the circuit board to modify a signal level in the discrete graphics card slot to a signal level in the PCIe device.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 19, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Ying Chih, Chao-Wen Cheng, Chun-Yi Liu
  • Publication number: 20220179468
    Abstract: In examples, a computer system comprises a first power supply having first and second power rails; a second power supply having a third power rail; a motherboard coupled to the first power rail; a central processing unit (CPU) coupled to the second power rail; a variable performance electronic component coupled to the third power rail; and a controller coupled to enable inputs of the first and second power supplies.
    Type: Application
    Filed: July 25, 2019
    Publication date: June 9, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Chien-Fa Huang, Roger A. Pearson, Chung Yu Chang
  • Publication number: 20220171446
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: June 2, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih