Patents by Inventor Chao-Wen Lay
Chao-Wen Lay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11895829Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.Type: GrantFiled: June 10, 2022Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Pei-Rou Jiang, Chao-Wen Lay
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Patent number: 11882690Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.Type: GrantFiled: June 10, 2022Date of Patent: January 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Pei-Rou Jiang, Chao-Wen Lay
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Publication number: 20240006232Abstract: A semiconductor device includes a semiconductor structure including a conductive feature therein, a bitline over the semiconductor structure, a spacer on a sidewall of the bitline, wherein the first spacer is made of SiCO, a dielectric layer over a top surface of the bitline; and a contact in contact with the dielectric layer and the spacer and connected to the conductive feature of the semiconductor structure.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Inventor: Chao-Wen LAY
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Publication number: 20230403845Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Inventors: PEI-ROU JIANG, CHAO-WEN LAY
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Publication number: 20230403846Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Inventors: PEI-ROU JIANG, CHAO-WEN LAY
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Patent number: 11804404Abstract: A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.Type: GrantFiled: October 14, 2021Date of Patent: October 31, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chao-Wen Lay
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Publication number: 20230123652Abstract: A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.Type: ApplicationFiled: October 14, 2021Publication date: April 20, 2023Inventor: Chao-Wen LAY
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Patent number: 11462548Abstract: A semiconductor device includes a semiconductor structure, a first dielectric layer and a plurality of multilayer stacks. The semiconductor structure includes conductive features therein. The first dielectric layer is on the semiconductor structure. The multilayer stacks are arranged on the first dielectric layer. Each of the multilayer stacks comprises a semiconductor layer over the first dielectric layer, a conductive layer over the semiconductor layer and a second dielectric layer over the conductive layer. The second dielectric layer includes a top portion and a bottom portion wider than the top portion.Type: GrantFiled: June 22, 2021Date of Patent: October 4, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chao-Wen Lay
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Patent number: 9659886Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.Type: GrantFiled: June 27, 2016Date of Patent: May 23, 2017Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Hung-Mo Wu, Ying-Cheng Chuang
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Publication number: 20160307859Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Hung-Mo Wu, Ying-Cheng Chuang
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Patent number: 9418949Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.Type: GrantFiled: September 17, 2013Date of Patent: August 16, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Hung-Mo Wu, Ying-Cheng Chuang
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Publication number: 20150076698Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Hung-Mo Wu, Ying-Cheng Chuang
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Patent number: 8921977Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: GrantFiled: December 21, 2011Date of Patent: December 30, 2014Assignee: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I Hsieh, Ching Kai Lin
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Patent number: 8658051Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: GrantFiled: May 12, 2008Date of Patent: February 25, 2014Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Wen-Bin Wu, Ya-Chih Wang, Chiang-Lin Shih, Chao-Wen Lay, Chih-Huang Wu
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Publication number: 20130161786Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I. Hsieh, Ching Kai Lin
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Patent number: 8222163Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.Type: GrantFiled: August 6, 2010Date of Patent: July 17, 2012Assignee: Nanya Technology Corp.Inventors: Chao-Wen Lay, Ching-Kai Lin
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Publication number: 20120034791Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Inventors: Chao-Wen Lay, Ching-Kai Lin
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Publication number: 20090233448Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: ApplicationFiled: May 12, 2008Publication date: September 17, 2009Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuo-Yao CHO, Wen-Bin WU, Ya-Chih WANG, Chiang-Lin SHIH, Chao-Wen LAY, Chih-Huang WU
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Publication number: 20090087978Abstract: An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures.Type: ApplicationFiled: December 18, 2007Publication date: April 2, 2009Inventors: Chao-Wen Lay, Jen-Jui Huang
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Patent number: 7078748Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned.Type: GrantFiled: June 14, 2004Date of Patent: July 18, 2006Assignees: Infineon Technologies AG, Nanya Technology CorporationInventors: Matthias Goldbach, Frank Jakubowski, Ralf Koepe, Chao-Wen Lay, Kristin Schupke, Michael Schmidt, Cheng-Chih Huang