Abstract: A PLL status detection circuit and its associated method are disclosed herein. The circuit and the method are used to detect a PLL clock generated by a PLL of a chip to determine a status of the PLL. The PLL status detection circuit includes a counter, a status analyzing circuit and a status storing circuit. The counter is configured to generate a count value by counting cycles of the PLL clock according to a control signal. The status analyzing circuit, which is coupled to the counter, is configured to analyze the count value according to the control signal to generate an analyzed result. The status storing circuit, which is coupled to the status analyzing circuit, is configured to store the analyzed result. The status storing circuit is coupled to a scan chain of the chip so that the analyzed result is transmitted via the scan chain.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: The present invention discloses a delay difference detection and adjustment device comprising: a first delay circuit including first delay units to receive and transmit a first clock; a second delay circuit including second delay units to receive and transmit a second clock; a storage circuit including storage units, each of which includes a data input end to receive the first clock and an operation clock reception end to receive the second clock, so that the storage circuit is operable to save a plurality of levels of the first clock according to the second clock; a delay control circuit to adjust the delay amount of the second delay circuit; and an analyzing circuit to generate an analysis result according to the cycle and levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first and second delay units.

Abstract: A multi-phase clock generation system and a clock calibration method thereof. The multi-phase clock generation system comprises an input module, a frequency division module and a control module. The input module inputs a reference clock signal with a clock period. The frequency division module according to the reference clock signal produces a phase clock signal with a frequency magnification relationship. The control module divides the phase clock signal into a plurality of clock intervals. There is a clock interval between two adjacent phase clock signals, and each of the plurality of clock intervals has a phase time delay. The control module controls a first phase clock signal of the plurality of phase clock signals to align with a last phase clock signal. The control module sequentially arranges each of the plurality of phase clock signals according to the phase time delay.

Abstract: The present invention discloses a phase-locked loop device and a clock calibration method thereof, wherein the phase-locked loop device comprises a first oscillating module, a second oscillating module, a comparison module and a control module. The first oscillating module generates a first clock signal. The second oscillating module generates a second clock signal. After comparing the first clock signal with the second clock signal, the comparison module generates a difference signal. According to the difference signal, the control module, electrically connected with the first oscillating module, the second oscillating module and the comparison module, interactively tunes the first clock signal and the second clock signal to be as close as possible.