Publication number: 20240036113
Abstract: A test circuit (300, 300?, 400, 500, 600, 700, 800), including: a test sequence providing module (301), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (303); a clock driving module (307, 407, 507, 607, 707, 807), configured to provide a clock signal (759) to the to-be-tested sequential device (303), which includes a first clock driving circuit (610, 710), wherein the first clock driving circuit (610, 710) includes: a plurality of first clock paths (421, 423) which respectively provide corresponding clock signals (759); and a logic unit (427, 715) which generates, based on at least part of the clock signals (759) provided by the plurality of first clock paths (421, 423), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (303); and a verification module (305, 405, 805), configured to verify an output of the to-be-tested sequential device (303).
Type:
Application
Filed:
January 6, 2022
Publication date:
February 1, 2024
Applicant:
SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Inventors:
Mo CHEN, Zhijun FAN, Jianbo LIU, Chao XU