Patents by Inventor Chao-Yen Huang
Chao-Yen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072498Abstract: A quick release module includes a support, a first release assembly and a connector. The support has an accommodation hole and a first lateral contact surface located at a periphery of the accommodation hole. The first release assembly includes a first holder. The first holder is slidably disposed on the support, and the first holder is movable towards or away from the first lateral contact surface so as to form an adjustable installation space between the first holder and the first lateral contact surface. The connector is disposed at the adjustable installation space. The connector is fixed by the first lateral contact surface and the first holder, and is removable from the adjustable installation space by sliding the first holder.Type: ApplicationFiled: November 10, 2022Publication date: February 29, 2024Inventors: CHAO YEN HU, Chin Luang Huang
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Patent number: 8997032Abstract: Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.Type: GrantFiled: April 16, 2013Date of Patent: March 31, 2015Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shi-Hao Chen, Tsung-Ying Tsai, Chao-Yen Huang
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Patent number: 8981818Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: GrantFiled: December 16, 2013Date of Patent: March 17, 2015Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Tai Wang, Chao-Yen Huang
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Patent number: 8970284Abstract: A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.Type: GrantFiled: March 1, 2012Date of Patent: March 3, 2015Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Tai Wang, Sheng-Tsai Huang, Chao-Yen Huang
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Patent number: 8933730Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: GrantFiled: December 16, 2013Date of Patent: January 13, 2015Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Tai Wang, Chao-Yen Huang
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Patent number: 8779739Abstract: A DC converter is provided for converting a first supply voltage into a second supply voltage. The first supply voltage is higher than the second supply voltage. The DC converter includes a driving stage and an output stage. The driving stage includes a modulation circuit, a pull-up driving unit, a pull-up unit, a pull-down driving unit, and a pull-down unit. The modulation circuit generates a control signal according to the second supply voltage. The pull-up driving unit generates a first P-type driving signal and a second P-type driving signal to the pull-up unit according to the control signal. The pull-down driving unit generates a first N-type driving signal and a second N-type driving signal to the pull-down unit according to the control signal.Type: GrantFiled: February 5, 2013Date of Patent: July 15, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yen Huang, Jung-Tsun Chuang
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Patent number: 8724269Abstract: ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.Type: GrantFiled: January 18, 2012Date of Patent: May 13, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Tai Wang, Sheng-Tsai Huang, Chao-Yen Huang
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Publication number: 20140103966Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Chao-Yen Huang
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Publication number: 20140103965Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Chao-Yen Huang
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Patent number: 8669803Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.Type: GrantFiled: February 21, 2013Date of Patent: March 11, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yen Huang, Jung-Tsun Chuang
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Patent number: 8633737Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: GrantFiled: March 1, 2012Date of Patent: January 21, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Tai Wang, Chao-Yen Huang
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Publication number: 20130283221Abstract: Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.Type: ApplicationFiled: April 16, 2013Publication date: October 24, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Shi-Hao Chen, Tsung-Ying Tsai, Chao-Yen Huang
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Publication number: 20120223767Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Chao-Yen Huang
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Publication number: 20120223759Abstract: A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Sheng-Tsai Huang, Chao-Yen Huang
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Publication number: 20120182654Abstract: ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Sheng-Tsai Huang, Chao-Yen Huang