Patents by Inventor Chao-Yen Lin
Chao-Yen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131808Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.Type: ApplicationFiled: December 7, 2022Publication date: April 25, 2024Inventors: TENG-YEN WANG, SHUN-SHENG KO, MIAO-CHANG WU, TUNG-YING LIN, CHAO-HONG HSU
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Publication number: 20240071362Abstract: In example implementations, a computing device is provided. The computing device includes a system management bus, a controller communicatively coupled to the system management bus, a noise generating component communicatively coupled to the controller, a noise cancellation codec communicatively coupled to the system management bus, and a speaker communicatively coupled to the noise cancellation codec. The operating parameters of the noise generating component are provided to the controller. The noise cancellation codec is to receive the operating parameters of the noise generating component from the controller via the system management bus and to generate a noise cancellation signal based on the operating parameters. The speaker outputs the noise cancellation signal to cancel noise generated by the noise generating component.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Chao-Wen Cheng, Tsung Yen Chen, Wen Shih Chen, Mo-Hsuan Lin, Juiching Chang
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Patent number: 9437478Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: September 6, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen, Ho-Yin Yiu
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Patent number: 9425134Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: August 23, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9355970Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: December 3, 2015Date of Patent: May 31, 2016Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9355975Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: May 31, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen, Chi-Chang Liao
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Publication number: 20160086896Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Patent number: 9209124Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: August 12, 2013Date of Patent: December 8, 2015Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9196594Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: GrantFiled: July 21, 2014Date of Patent: November 24, 2015Assignee: XINTEC INC.Inventors: Chao-Yen Lin, Yi-Hang Lin
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Patent number: 9030011Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: GrantFiled: August 5, 2013Date of Patent: May 12, 2015Assignee: Xintec Inc.Inventors: Chao-Yen Lin, Yi-Hang Lin
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Patent number: 8963312Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: February 24, 2015Assignee: Xintec, Inc.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 8952501Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: GrantFiled: July 24, 2013Date of Patent: February 10, 2015Assignee: Xintec, Inc.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Publication number: 20140332968Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20140332983Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20140332908Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN, Ho-Yin YIU
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Publication number: 20140332969Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN, Chi-Chang LIAO
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Publication number: 20140328523Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: ApplicationFiled: July 21, 2014Publication date: November 6, 2014Inventors: Chao-Yen LIN, Yi-Hang LIN
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Publication number: 20140054786Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: ApplicationFiled: August 12, 2013Publication date: February 27, 2014Applicant: XINTEC INC.Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20130320532Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: ApplicationFiled: August 5, 2013Publication date: December 5, 2013Applicant: XINTEC INC.Inventors: Chao-Yen LIN, Yi-Hang LIN
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Publication number: 20130307125Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: XINTEC INC.Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN