Abstract: A semiconductor device includes a drain electrode, a substrate, a first and a source contacts, a first and second gate electrodes, a gate connection structure and a gate insulation layer. The first and second source contacts are located on the substrate. The first and second gate electrodes are located between the first and second source contacts. The gate connection structure is located between the first and second gate electrodes and respectively connects the first gate electrode and the second gate electrode. The gate insulation layer surrounds the first and second gate electrodes, and the gate connection structure. The gate insulation layer includes an extension portion located between the first and second gate electrodes. An area of a vertical projection of the gate connection structure on the substrate is smaller than an area of a vertical projection of the extension portion of the gate insulation layer.

Abstract: A power diode device includes a substrate. The substrate includes a core layer of a first conductive type, a first diffusion layer of the first conductive type, a second diffusion layer of a second conductive type, and a heavily doped region of the second conductive type. The core layer is located between the first diffusion layer and the second diffusion layer. A thickness of the core layer is greater than that of the second diffusion layer. The heavily doped region is located in the second diffusion layer and extends toward the core layer to form a PN junction between the heavily doped region and the core layer. A method for manufacturing the power diode device is also provided.

Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.

Abstract: A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal; a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.

Abstract: A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal: a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.

Abstract: The present disclosure provides a lightweight tile. The lightweight tile has a tile body and a lacquer layer overlaying on the tile body. The tile body is composed of a rigid foamed resin having a plurality of void cells. The density of the rigid foamed resin is 0.2 to 0.45 g/cm3. The lightweight tile provided in the present disclosure is less dense than the conventional ceramic tiles. In addition, the heat insulation and sound insulation of the lightweight tile are excellent.