Patents by Inventor Chao-Yi Lan

Chao-Yi Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141480
    Abstract: Provided is a dual deposition chamber apparatus for producing silicon material, the apparatus including a furnace, a cooling jacket, a deposition device, and a vacuum extraction device. The cooling jacket communicates with the furnace, defines a space above the furnace, and includes an opening communicating with the space. The deposition device includes at least one first deposition substrate and at least one second deposition substrate. The at least one first deposition substrate and the at least one second deposition substrate are arranged side by side in the space, and respectively include a first inner wall surface and a second inner wall surface inclined downwards relative to a vertical axis. An uneven area is formed on the first inner wall surface and the second inner wall surface. The vacuum extraction device communicates with the opening of the cooling jacket.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Chung-Wen LAN, Wen-Yi CHIU, Chao-Kun HSIEH, Chao-Hsiang HSIEH
  • Patent number: 6563154
    Abstract: An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630° C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560° C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl3. Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: May 13, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Chieh Chang, Yu-Jen Yu, Te-Fu Tseng, Chao-Yi Lan
  • Patent number: 6344369
    Abstract: A process for forming a color image sensor cell, in which a bonding pad structure is protected from exposure to alkaline developer solution, used for definition of color filter elements, and also used to open a contact hole to the bonding pad structure, has been developed. The process features the use of a passivation layer, comprised of an overlying silicon nitride layer, and an underlying silicon oxide layer, located on the top surface of the bonding pad structure. The passivation layer protects the underlying bond pad structure from alkaline developer solutions used to define overlying color filter elements, of the color image sensor cell. After definition of the color filter elements the contact hole opening to the bond pad is finalized using a dry etching procedure, applied to the passivation layer.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: February 5, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Mei Huang, Chao-Yi Lan, Hsiao-Ping Chang, Chia-Kung Chang
  • Patent number: 6214717
    Abstract: A method is disclosed for improving the bonding strength of wire bonds on semiconductor chips. Aluminum-silicon-copper is employed as the metal for wire bonding-pads. Openings are formed in the passivation layer over the bonding-pads. The exposed metal in the openings is treated with a fluorine containing F-plasma. A thin passivation film, with C, F, and O content is formed over the metal bonding pads. This protective film prevents the formation of pitting and staining of the bonding-pads when the wafer is subjected to repeated developing solutions during the color filter process performed for the CMOS image sensors, for example. Consequently, the wire bonds formed during the packaging of the chips are stronger and more reliable.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: April 10, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Yi Lan, Shean-Ren Horng, Yang-Tung Fan, Chih-Kang Chiu
  • Patent number: 5874333
    Abstract: An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630.degree. C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560.degree. C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl.sub.3. Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: February 23, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chang, Yu-Jen Yu, Te-Fu Tseng, Chao-Yi Lan
  • Patent number: 5854134
    Abstract: The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: December 29, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chao-Yi Lan, Shean-Ren Horng, Yun-Hung Shen, Hung-Jen Tsai