Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.

Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: The present invention relates to the treatment of herpes simplex virus (HSV) infection using an anti-HSV antibody. In particular, the anti-HSV antibody specifically binds to the glycoprotein D (gD) of herpes simplex virus-1 (HSV-1) and herpes simplex virus-2 (HSV-2). The treatment of the present invention is effective against drug-resistant and/or recurrent HSV infection.

Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.

Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.