Patents by Inventor Chao-Yu Chang

Chao-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983271
    Abstract: A processor may generate an enforcement point. The enforcement point may include one or more adversarial detection models. The processor may receive user input data. The processor may analyze, at the enforcement point, the user input data. The processor may determine, from the analyzing, whether there is an adversarial attack in the user input data. The processor may generate an alert based on the determining.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 14, 2024
    Assignee: International Business Machines Corporation
    Inventors: Bruno dos Santos Silva, Cheng-Ta Lee, Ron Williams, Bo-Yu Kuo, Chao-Min Chang, Sridhar Muppidi
  • Publication number: 20240154025
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240096388
    Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20230187950
    Abstract: An adapter for a charging cradle includes: a perimeter wall defining a channel between first and second ends; a first device interface on an inner surface of the perimeter wall in communication with the first end, the first device interface configured to receive and align a first mobile device configuration with the charging cradle; a second device interface on the inner surface of the perimeter wall in communication with the second end, the second device interface configured to receive and align a second mobile device configuration with the charging cradle; a cradle interface on an outer surface of the perimeter wall, and configured to couple the adapter to the charging cradle in one of (i) a first orientation to expose a connector of the charging cradle via the first end of the channel, and (ii) a second orientation to expose the connector via the second end of the channel.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Mu-Kai Shen, Liao-Hsun Chen, Chao Yu Chang
  • Patent number: 6957116
    Abstract: A quality assurance system and method for use between a service provider having a sequence of process stages and a quality assurance stage, and a control center. The service provider performs a plurality of processes on goods at the process stages, transfers engineering data corresponding to the processes to the control center via Internet, and holds the goods at the quality assurance. The control center compares the engineering data with a standard specification, and transfers a confirmation message to the service provider if the engineering data conforms to the standard specification. The service provider may ship the goods to customers after the confirmation message is received.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: October 18, 2005
    Assignee: Taiwan Semiconductor Manufcturing Co., Ltd.
    Inventors: Jung-Yi Tsai, Chao-Yu Chang, Chui-Chung Chiu, Shu-Jung Tseng
  • Publication number: 20050075749
    Abstract: A quality assurance system and method for use between a service provider having a sequence of process stages and a quality assurance stage, and a control center. The service provider performs a plurality of processes on goods at the process stages, transfers engineering data corresponding to the processes to the control center via Internet, and holds the goods at the quality assurance. The control center compares the engineering data with a standard specification, and transfers a confirmation message to the service provider if the engineering data conforms to the standard specification. The service provider may ship the goods to customers after the confirmation message is received.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 7, 2005
    Inventors: Jung-Yi Tsai, Chao-Yu Chang, Chui-Chung Chiu, Shu-Jung Tseng
  • Patent number: 6216397
    Abstract: A modular partition is composed of a plurality of posts, panels and shelves detachably interconnected therebetween. Disposing different specifications and varied amounts of the panels between the posts according to specific requirement can form partition walls with varied arrangements. The shelves disposed between any two of the walls can be mounted on any one of the panels to obtain desired heights.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: April 17, 2001
    Inventor: Chao-Yu Chang