Patents by Inventor Chao-Yu Hu

Chao-Yu Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10489879
    Abstract: An image processing chip and an image processing system are provided. The image processing chip includes a first image end, a second image end, an image processing block and a multiplexer. The first image end receives at least one first image data packet. The image processing block is used to convert the at least one first image data packet into at least one second image data packet. The multiplexer has a first input end coupled to the first image end, a second input end coupled to the image processing block, and an output end coupled to the second image end. When the image processing chip operates in a first mode, the multiplexer is coupled to the first input end and the output end to transmit the at least one first image data packet from the first image end to the second image through the multiplexer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 26, 2019
    Assignee: Altek Semiconductor Corp.
    Inventor: Chao-Yu Hu
  • Publication number: 20190035048
    Abstract: An image processing chip and an image processing system are provided. The image processing chip includes a first image end, a second image end, an image processing block and a multiplexer. The first image end receives at least one first image data packet. The image processing block is used to convert the at least one first image data packet into at least one second image data packet. The multiplexer has a first input end coupled to the first image end, a second input end coupled to the image processing block, and an output end coupled to the second image end. When the image processing chip operates in a first mode, the multiplexer is coupled to the first input end and the output end to transmit the at least one first image data packet from the first image end to the second image through the multiplexer.
    Type: Application
    Filed: August 30, 2017
    Publication date: January 31, 2019
    Applicant: Altek Semiconductor Corp.
    Inventor: Chao-Yu Hu
  • Patent number: 9864521
    Abstract: The invention provides a method of managing SDIO commands at a host device and a peripheral device. The host device connected to the peripheral device by a bus comprising a command transmission line and a data transmission line, both of which are arranged to transmit single end signal. The host device converts operation requests into converted commands and combines a first SDIO complied data packet with the converted commands to generate a first combined data packet. Then, the host device transmits the first combined data packet through the data transmission line, wherein the first combined data packet comprises a first header for indicating whether the first combined data packet comprises the converted commands. After receiving the first combined data packet, the peripheral device parses the first combined data packet to obtain the converted commands, and then performs processing procedures according to the converted commands.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 9, 2018
    Assignee: MEDIATEK INC.
    Inventor: Chao-Yu Hu
  • Publication number: 20150120964
    Abstract: The invention provides a method of managing SDIO commands at a host device and a peripheral device. The host device connected to the peripheral device by a bus comprising a command transmission line and a data transmission line, both of which are arranged to transmit single end signal. The host device converts operation requests into converted commands and combines a first SDIO complied data packet with the converted commands to generate a first combined data packet. Then, the host device transmits the first combined data packet through the data transmission line, wherein the first combined data packet comprises a first header for indicating whether the first combined data packet comprises the converted commands. After receiving the first combined data packet, the peripheral device parses the first combined data packet to obtain the converted commands, and then performs processing procedures according to the converted commands.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Inventor: Chao-Yu Hu
  • Patent number: 7840722
    Abstract: A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 23, 2010
    Assignee: Ralink Technology Corp.
    Inventors: Cheok-Yan Goh, Chao-Yu Hu
  • Publication number: 20090172202
    Abstract: A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.
    Type: Application
    Filed: November 4, 2008
    Publication date: July 2, 2009
    Inventors: Check-Yan Goh, Chao-Yu Hu
  • Publication number: 20090164678
    Abstract: The invention provides a method of managing SDIO commands. Firstly, before a first packet complying with a first SDIO data format is transmitted, an operation request is converted into a converted command. The operation request is originally set to be converted into a command complying with a SDIO command format. Then, the fist packet and the converted command are combined to generate a first combined packet. Afterward, the first combined packet is transmitted. After the first combined packet is received, the first combined packet is parsed to obtain the converted command. Finally, a processing procedure is performed according to the converted command.
    Type: Application
    Filed: October 7, 2008
    Publication date: June 25, 2009
    Inventor: Chao-Yu HU
  • Patent number: 6959066
    Abstract: The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: October 25, 2005
    Assignee: Elan Microelectronics Corp.
    Inventors: Jung-Chih Wang, Chao-Yu Hu
  • Publication number: 20030184350
    Abstract: The present invention relates to a programmable frequency divider, comprising one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.
    Type: Application
    Filed: March 21, 2003
    Publication date: October 2, 2003
    Applicant: Elan Microelectronics Corp.
    Inventors: Jung-Chih Wang, Chao-Yu Hu