Patents by Inventor Chao-Yuan Su
Chao-Yuan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691749Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.Type: GrantFiled: August 12, 2014Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yuan Su, Chung-Yi Lin
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Publication number: 20150115362Abstract: A lateral diffused N-type metal oxide semiconductor device includes a semiconductor substrate, an epi-layer on the semiconductor substrate, a patterned isolation layer on the epi-layer, a N-type double diffused drain (NDDD) region in a first active region of the patterned isolation layer, a N+ heavily doped drain region disposed in the NDDD region, a P-body diffused region disposed in a second active region of the patterned isolation layer, a neighboring pair of a N+ heavily doped source region and a P+ heavily doped source region disposed in the P-body diffused region, a first gate structure disposed above a channel region of the patterned isolation layer and a second gate structure disposed above the second active region. The second gate structure and the first gate structure are spaced at a predetermined distance. A making method of the NDDD region includes using an ion implant and an epitaxy layer doping.Type: ApplicationFiled: June 13, 2014Publication date: April 30, 2015Inventors: Chao-Yuan Su, Ching-Yi Wu, Hung-Bin Chen, Chun-Yen Chang
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Publication number: 20150115361Abstract: A lateral diffused N-type metal oxide semiconductor device includes a semiconductor substrate, an epi-layer on the semiconductor substrate, a patterned isolation layer on the epi-layer, a N-type double diffused drain (NDDD) region in a first active region of the patterned isolation layer, a N+ heavily doped drain region disposed in the NDDD region, a P-body diffused region disposed in a second active region of the patterned isolation layer, a neighboring pair of a N+ heavily doped source region and a P+ heavily doped source region disposed in the P-body diffused region, a first gate structure disposed above a channel region of the patterned isolation layer and a second gate structure disposed above the second active region. The second gate structure and the first gate structure are spaced at a predetermined distance.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicants: Himax Technologies Limited, National Chiao Tung University, Himax Analogic, Inc.Inventors: Chao-Yuan Su, Ching-Yi Wu, Hung-Bin Chen, Chun-Yen Chang
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Publication number: 20140346644Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Inventors: Chao-Yuan Su, Chung-Yi Lin
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Patent number: 8829653Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.Type: GrantFiled: December 4, 2013Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yuan Su, Chung-Yi Lin
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Publication number: 20140087492Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.Type: ApplicationFiled: December 4, 2013Publication date: March 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chao-Yuan Su, Chung-Yi Lin
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Patent number: 8629563Abstract: Integrated circuit structures and methods are provided. According to an embodiment, a circuit structure includes a die and an anisotropic conducting film (ACF). The die comprises a through via, and the through via protrudes from a surface of the die. A cross-sectional area of the through via in the surface of the die is equal to a cross-sectional area of a protruding portion of the through via in a plane parallel to the surface of the die. The ACF adjoins the surface of the die, and the protruding portion of the through via penetrates the ACF.Type: GrantFiled: February 8, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chao-Yuan Su
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Patent number: 8624346Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.Type: GrantFiled: January 3, 2006Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yuan Su, Chung-Yi Lin
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Patent number: 8497584Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: GrantFiled: March 26, 2004Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Publication number: 20120146238Abstract: Integrated circuit structures and methods are provided. According to an embodiment, a circuit structure includes a die and an anisotropic conducting film (ACF). The die comprises a through via, and the through via protrudes from a surface of the die. A cross-sectional area of the through via in the surface of the die is equal to a cross-sectional area of a protruding portion of the through via in a plane parallel to the surface of the die. The ACF adjoins the surface of the die, and the protruding portion of the through via penetrates the ACF.Type: ApplicationFiled: February 8, 2012Publication date: June 14, 2012Inventor: Chao-Yuan Su
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Patent number: 8124458Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.Type: GrantFiled: September 16, 2010Date of Patent: February 28, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chao-Yuan Su
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Patent number: 7906425Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: October 13, 2006Date of Patent: March 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 7892962Abstract: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense.Type: GrantFiled: September 5, 2007Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chao-Yuan Su
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Publication number: 20110014749Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.Type: ApplicationFiled: September 16, 2010Publication date: January 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chao-Yuan Su
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Patent number: 7825517Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.Type: GrantFiled: July 16, 2007Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chao-Yuan Su
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Patent number: 7719076Abstract: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.Type: GrantFiled: August 10, 2007Date of Patent: May 18, 2010Assignee: United Microelectronics Corp.Inventors: Shih-Ming Shu, Chih-Jen Huang, Tun-Jen Cheng, Chao-Yuan Su
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Patent number: 7709908Abstract: A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.Type: GrantFiled: August 10, 2007Date of Patent: May 4, 2010Assignee: United Microelectronics Corp.Inventors: Chao-Yuan Su, Wei-Lun Hsu, Ching-Ming Lee, Chih-Jen Huang, Te-Yuan Wu, Chun-Hsiung Peng
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Publication number: 20090111252Abstract: A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Jen Huang, Ching-Ming Lee, Wei-Lun Hsu, Chao-Yuan Su, Chun-Hsiung Peng
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Publication number: 20090057896Abstract: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense.Type: ApplicationFiled: September 5, 2007Publication date: March 5, 2009Inventor: Chao-Yuan Su
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Publication number: 20090039425Abstract: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.Type: ApplicationFiled: August 10, 2007Publication date: February 12, 2009Inventors: Shih-Ming Shu, Chih-Jen Huang, Tun-Jen Cheng, Chao-Yuan Su