Abstract: In an integrated circuit design, slack on a signal path of an integrated circuit design can be apportioned in order to accelerate design refinement. According to one method, timing analysis of the signal path of the integrated circuit design is performed. Estimated (as opposed to actual) slack on the signal path is determined through content-based analysis of components of the signal path based on elimination of timing inefficiencies within the components. The estimated slack is then proportionally apportioned among the components of the signal path for use in a subsequent iteration of design refinement.

Abstract: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Abstract: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Abstract: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

Abstract: An in-situ fabrication method for a silicon solar cell includes the following steps: pretreating a silicon chip; placing the pretreated silicon chip in an implantation chamber of a plasma immersion ion implantation machine; completing the preparation of black silicon via a plasma immersion ion implantation process; making a PN junction and forming a passivation layer on the black silicon; after making the PN junction and forming the passivation layer, removing the black silicon from the plasma immersion ion implantation machine; preparing a metal back electrode on the back of the black silicon; preparing a metal grid on the passivation layer; obtaining a solar cell after encapsulation. Said method enables black silicon preparation, PN junction preparation, and passivation layer formation in-situ, greatly reducing the amount of equipment needed for the preparation of solar cells and the preparation cost. In addition, the method is simple and easy to control.

Abstract: A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.

Abstract: A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.

Abstract: An in-situ fabrication method for a silicon solar cell includes the following steps: pretreating a silicon chip; placing the pretreated silicon chip in an implantation chamber of a plasma immersion ion implantation machine; completing the preparation of black silicon via a plasma immersion ion implantation process; making a PN junction and forming a passivation layer on the black silicon; after making the PN junction and forming the passivation layer, removing the black silicon from the plasma immersion ion implantation machine; preparing a metal back electrode on the back of the black silicon; preparing a metal grid on the passivation layer; obtaining a solar cell after encapsulation. Said method enables black silicon preparation, PN junction preparation, and passivation layer formation in-situ, greatly reducing the amount of equipment needed for the preparation of solar cells and the preparation cost. In addition, the method is simple and easy to control.

Abstract: A black silicon solar cell includes a metal back electrode, the crystal silicon, a black silicon layer, a passivation layer and a metal gate; wherein, the metal back electrode is located on the back surface of the crystal silicon, the black silicon layer is located on the crystal silicon, the passivation layer is located on the black silicon layer, the metal gate is located on the passivation layer. The fabrication method includes: carrying out pretreatment of the silicon wafer; preparing the black silicon layer on the surface of the pretreated silicon wafer by using plasma immersion ion implantation technology; preparing an emitter on the black silicon layer, and carrying out passivation treatment on the emitter to form the passivation layer; respectively preparing the metal back electrode and the metal gate on the back surface of the single crystal silicon wafer and the passivation layer, respectively.