Patents by Inventor Chaochao Fu

Chaochao Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9570595
    Abstract: A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: February 14, 2017
    Assignee: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Chaochao Fu, Wei Zhang, Shi-Li Zhang
  • Publication number: 20160190293
    Abstract: A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 30, 2016
    Applicant: Fudan University
    Inventors: Dongping Wu, Chaochao Fu, Wei Zhang, Shili Zhang
  • Publication number: 20160079389
    Abstract: The invention presents a preparation method of semiconductor device, form an amorphous region in the semiconductor substrate, then form the source/drain region of the semiconductor device in the semiconductor substrate, the amorphous region can restrain the generation of end-of-range defects of the source/drain region, then can lower well the current leakage between the semiconductor device source/drain region and the semiconductor substrate; besides, after the dummy gate structure is eliminated, form a short channel inhibition region in the channel region; it can restrain the short-channel effect of the semiconductor device and satisfy the requirement of keeping narrowing the feature size of the device.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 17, 2016
    Inventors: Dongping Wu, Peng Xu, Xiangbiao Zhou, Chaochao Fu