Patents by Inventor Chaochao SUN

Chaochao SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066504
    Abstract: The present disclosure provides a thin film transistor, a manufacturing method thereof, and a display device, and the thin film transistor of the present disclosure includes: a substrate; a gate, a gate insulating layer, an active layer, a source and drain layer sequentially provided on the substrate, and the source and drain layer is correspondingly provided at a first source contact region and a first drain contact region of the active layer. A planarization layer is provided between the gate insulating layer and the substrate, the planarization layer is in a same layer as the gate and in direct contact with the gate, and an upper surface of the planarization layer is flush with an upper surface of the gate.
    Type: Application
    Filed: March 18, 2020
    Publication date: March 4, 2021
    Inventors: Yanwei REN, Tianlei SHI, Wulijibaier TANG, Jingyi XU, Yanan YU, Chaochao SUN, Min LIU
  • Publication number: 20200312217
    Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.
    Type: Application
    Filed: September 20, 2018
    Publication date: October 1, 2020
    Inventors: Yanwei REN, Yezhou FANG, Jingyi XU, Xin ZHAO, Min LIU, Chaochao SUN
  • Publication number: 20200241369
    Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.
    Type: Application
    Filed: August 7, 2017
    Publication date: July 30, 2020
    Inventors: Duolong DING, Huafeng LIU, Shengwei ZHAO, Chaochao SUN, Chao WANG, Jingping LV, Meng YANG, Lei YANG, Chongliang HU, Lin XIE, Bule SHUN, Shimin SUN
  • Patent number: 10564772
    Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 18, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Chaochao Sun, Huafeng Liu, Shengwei Zhao, Kai Zhang, Lei Yang, Lulu Ye, Jingping Lv, Chao Wang, Chongliang Hu, Meng Yang, Duolong Ding, Bule Shun, Lin Xie, Yao Li, Shimin Sun
  • Publication number: 20190318682
    Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.
    Type: Application
    Filed: September 20, 2018
    Publication date: October 17, 2019
    Inventors: Yanwei REN, Yezhou FANG, Jingyi XU, Xin ZHAO, Min LIU, Chaochao SUN
  • Patent number: 10325943
    Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
  • Patent number: 10192993
    Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanwei Ren, Chaochao Sun, Kunpeng Zhang, Yezhou Fang, Jingyi Xu
  • Patent number: 10120256
    Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lulu Ye, Huafeng Liu, Jingping Lv, Lei Yang, Meng Yang, Kai Zhang, Chao Wang, Chaochao Sun, Shengwei Zhao
  • Publication number: 20180197901
    Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.
    Type: Application
    Filed: December 12, 2016
    Publication date: July 12, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
  • Publication number: 20180190830
    Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.
    Type: Application
    Filed: September 14, 2017
    Publication date: July 5, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanwei REN, Chaochao SUN, Kunpeng ZHANG, Yezhou FANG, Jingyi XU
  • Publication number: 20170329163
    Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.
    Type: Application
    Filed: December 31, 2015
    Publication date: November 16, 2017
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD
    Inventors: Lulu YE, Huafeng LIU, Jingping LV, Lei YANG, Meng YANG, Kai ZHANG, Chao WANG, Chaochao SUN, Shengwei ZHAO
  • Publication number: 20170205953
    Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.
    Type: Application
    Filed: August 10, 2016
    Publication date: July 20, 2017
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Chaochao SUN, Huafeng LIU, Shengwei ZHAO, Kai ZHANG, Lei YANG, Lulu YE, Jingping LV, Chao WANG, Chongliang HU, Meng YANG, Duolong DING, Bule SHUN, Lin XIE, Yao LI, Shimin SUN