Patents by Inventor Chaochao SUN
Chaochao SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12065682Abstract: The present invention belongs to the bioengineering field, and relates to a method for fermentation production of L-theanine by using an Escherichia coli genetically engineered bacterium. The engineered bacterium is obtained by serving a strain as an original strain, wherein the strain is obtained after performing a single copy of T7RNAP, a dual copy of gmas, xylR knockout, and sucCD knockout on an Escherichia coli W3110 genome, and by integrating genes xfp, pta, acs, gltA, and ppc, and knocking out ackA on the genome. The present invention has a high yield, and stable production performance; after 20-25 h, L-theanine has a titer of 75-80 g/L, and the yield is up to 52-55%. The fermentation broth is purified by membrane separation in combination with a cation-anion resin series technique. Moreover, the one-step crystallization yield is 72.3% and the L-theanine final product has a purity of 99%.Type: GrantFiled: August 17, 2022Date of Patent: August 20, 2024Assignees: Henan Julong Biological Engineering Co., Ltd, Tianjin University of Science and TechnologyInventors: Xiaoguang Fan, Xiaodong Liu, Jing Li, Ning Chen, Bochao Liu, Shuai Liu, Chaochao Sun, Yongchao Liu, Jiajia Teng, Mengtao Zhang, Yuanqing Ji, Yuhang Zhou, Qingyang Xu
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Publication number: 20230109256Abstract: The present invention belongs to the bioengineering field, and relates to a method for fermentation production of L-theanine by using an Escherichia coli genetically engineered bacterium. The engineered bacterium is obtained by serving a strain as an original strain, wherein the strain is obtained after performing a single copy of T7RNAP, a dual copy of gmas, xylR knockout, and sucCD knockout on an Escherichia coli W3110 genome, and by integrating genes xfp, pta, acs, gltA, and ppc, and knocking out ackA on the genome. The present invention has a high yield, and stable production performance; after 20-25 h, L-theanine has a titer of 75-80 g/L, and the yield is up to 52-55%. The fermentation broth is purified by membrane separation in combination with a cation-anion resin series technique. Moreover, the one-step crystallization yield is 72.3% and the L-theanine final product has a purity of 99%.Type: ApplicationFiled: August 17, 2022Publication date: April 6, 2023Inventors: Xiaoguang Fan, Xiaodong Liu, Jing Li, Ning Chen, Bochao Liu, Shuai Liu, Chaochao Sun, Yongchao Liu, Jiajia Teng, Mengtao Zhang, Yuanqing Ji, Yuhang Zhou, Qingyang Xu
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Patent number: 11453898Abstract: The present invention belongs to the bioengineering field, and relates to a method for fermentation production of L-theanine by using an Escherichia coli genetically engineered bacterium. The engineered bacterium is obtained by serving a strain as an original strain, wherein the strain is obtained after performing a single copy of T7RNAP, a dual copy of gmas, xylR knockout, and sucCD knockout on an Escherichia coli W3110 genome, and by integrating genes xfp, pta, acs, gltA, and ppc, and knocking out ackA on the genome. The present invention has a high yield, and stable production performance; after 20-25 h, L-theanine has a titer of 75-80 g/L, and the yield is up to 52-55%. The fermentation broth is purified by membrane separation in combination with a cation-anion resin series technique. Moreover, the one-step crystallization yield is 72.3% and the L-theanine final product has a purity of 99%.Type: GrantFiled: December 31, 2021Date of Patent: September 27, 2022Assignees: Henan Julong Biological Engineering Co., Ltd, Tianjin University of Science and TechnologyInventors: Xiaoguang Fan, Xiaodong Liu, Jing Li, Ning Chen, Bochao Liu, Shuai Liu, Chaochao Sun, Yongchao Liu, Jiajia Teng, Mengtao Zhang, Yuanqing Ji, Yuhang Zhou, Qingyang Xu
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Patent number: 11411072Abstract: Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.Type: GrantFiled: April 25, 2019Date of Patent: August 9, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Huafeng Liu, Shengwei Zhao, Chaochao Sun, Chao Wang, Jingping Lv, Lin Xie, Guoqing Zhou, Panpan Zhang, Tengfei Wang, Hsinghua Pan, Lele Li, Zhiqiang Chang, Shaocong Dang, Shijie Mu, Zhen Wang
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Patent number: 11237440Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.Type: GrantFiled: August 7, 2017Date of Patent: February 1, 2022Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Duolong Ding, Huafeng Liu, Shengwei Zhao, Chaochao Sun, Chao Wang, Jingping Lv, Meng Yang, Lei Yang, Chongliang Hu, Lin Xie, Bule Shun, Shimin Sun
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Publication number: 20210376057Abstract: Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.Type: ApplicationFiled: April 25, 2019Publication date: December 2, 2021Inventors: Huafeng LIU, Shengwei ZHAO, Chaochao SUN, Chao WANG, Jingping LV, Lin XIE, Guoqing ZHOU, Panpan ZHANG, Tengfei WANG, Hsinghua PAN, Lele LI, Zhiqiang CHANG, Shaocong DANG, Shijie MU, Zhen WANG
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Patent number: 11093099Abstract: The present application discloses a first display substrate including a plurality of core-coil assemblies configured to detect a touch. Each of the plurality of core-coil assemblies includes a first base substrate; a core layer on the first base substrate and including a plurality of magnetic permeable cores substantially along a first direction and spaced apart from each other, each of the plurality of magnetic permeable cores substantially along a second direction; and a conductive coil wound around the plurality of magnetic permeable cores for multiple turns and insulated from the core layer.Type: GrantFiled: June 30, 2017Date of Patent: August 17, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.Inventors: Duolong Ding, Huafeng Liu, Shengwei Zhao, Chaochao Sun, Chao Wang, Jingping Lv, Meng Yang, Lei Yang, Chongliang Hu, Bule Shun, Lin Xie
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Publication number: 20210208712Abstract: The present application discloses a first display substrate including a plurality of core-coil assemblies configured to detect a touch. Each of the plurality of core-coil assemblies includes a first base substrate; a core layer on the first base substrate and including a plurality of magnetic permeable cores substantially along a first direction and spaced apart from each other, each of the plurality of magnetic permeable cores substantially along a second direction; and a conductive coil wound around the plurality of magnetic permeable cores for multiple turns and insulated from the core layer.Type: ApplicationFiled: June 30, 2017Publication date: July 8, 2021Applicants: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.Inventors: Duolong Ding, Huafeng Liu, Shengwei Zhao, Chaochao Sun, Chao Wang, Jingping Lv, Meng Yang, Lei Yang, Chongliang Hu, Bule Shun, Lin Xie
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Patent number: 11004381Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.Type: GrantFiled: September 20, 2018Date of Patent: May 11, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yanwei Ren, Yezhou Fang, Jingyi Xu, Xin Zhao, Min Liu, Chaochao Sun
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Publication number: 20210066504Abstract: The present disclosure provides a thin film transistor, a manufacturing method thereof, and a display device, and the thin film transistor of the present disclosure includes: a substrate; a gate, a gate insulating layer, an active layer, a source and drain layer sequentially provided on the substrate, and the source and drain layer is correspondingly provided at a first source contact region and a first drain contact region of the active layer. A planarization layer is provided between the gate insulating layer and the substrate, the planarization layer is in a same layer as the gate and in direct contact with the gate, and an upper surface of the planarization layer is flush with an upper surface of the gate.Type: ApplicationFiled: March 18, 2020Publication date: March 4, 2021Inventors: Yanwei REN, Tianlei SHI, Wulijibaier TANG, Jingyi XU, Yanan YU, Chaochao SUN, Min LIU
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Publication number: 20200312217Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.Type: ApplicationFiled: September 20, 2018Publication date: October 1, 2020Inventors: Yanwei REN, Yezhou FANG, Jingyi XU, Xin ZHAO, Min LIU, Chaochao SUN
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Publication number: 20200241369Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.Type: ApplicationFiled: August 7, 2017Publication date: July 30, 2020Inventors: Duolong DING, Huafeng LIU, Shengwei ZHAO, Chaochao SUN, Chao WANG, Jingping LV, Meng YANG, Lei YANG, Chongliang HU, Lin XIE, Bule SHUN, Shimin SUN
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Patent number: 10564772Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.Type: GrantFiled: August 10, 2016Date of Patent: February 18, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Chaochao Sun, Huafeng Liu, Shengwei Zhao, Kai Zhang, Lei Yang, Lulu Ye, Jingping Lv, Chao Wang, Chongliang Hu, Meng Yang, Duolong Ding, Bule Shun, Lin Xie, Yao Li, Shimin Sun
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Publication number: 20190318682Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.Type: ApplicationFiled: September 20, 2018Publication date: October 17, 2019Inventors: Yanwei REN, Yezhou FANG, Jingyi XU, Xin ZHAO, Min LIU, Chaochao SUN
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Patent number: 10325943Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.Type: GrantFiled: December 12, 2016Date of Patent: June 18, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
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Patent number: 10192993Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.Type: GrantFiled: September 14, 2017Date of Patent: January 29, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Yanwei Ren, Chaochao Sun, Kunpeng Zhang, Yezhou Fang, Jingyi Xu
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Patent number: 10120256Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.Type: GrantFiled: December 31, 2015Date of Patent: November 6, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Lulu Ye, Huafeng Liu, Jingping Lv, Lei Yang, Meng Yang, Kai Zhang, Chao Wang, Chaochao Sun, Shengwei Zhao
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Publication number: 20180197901Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.Type: ApplicationFiled: December 12, 2016Publication date: July 12, 2018Applicants: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
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THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
Publication number: 20180190830Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.Type: ApplicationFiled: September 14, 2017Publication date: July 5, 2018Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Yanwei REN, Chaochao SUN, Kunpeng ZHANG, Yezhou FANG, Jingyi XU -
Patent number: D1029185Type: GrantFiled: April 22, 2022Date of Patent: May 28, 2024Assignee: Huaian Hohear Tech. Co., Ltd.Inventors: Han Sun, Li Chen, Chaochao Sun, Kai Liu, Dongdong Zhang, Jiajie Yan, Wentao Yan, Yueyue Qian, Zhiyu Chen