Patents by Inventor Chaodan Deng

Chaodan Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7724078
    Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Chaodan Deng, Thomas P. Thomas
  • Publication number: 20090079406
    Abstract: A voltage regulator includes an amplifier having first and second outputs, a feedback path coupled between a first input and the first output of the amplifier, and a feed-forward path between the second output of the amplifier and a switch coupled to a reference potential. In operation, a first control signal from the second output of the amplifier is generated based on a comparison of a reference signal and a feedback signal into the first input of the amplifier. The first control signal controls the switch to maintain a substantially constant supply voltage. A second control signal is generated along the feedback path to control controls the amount of supply voltage.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Chaodan Deng, Nasser A. Kurd, George Geannopoulos
  • Patent number: 7429881
    Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: September 30, 2008
    Assignee: Intel Corporation
    Inventors: Chaodan Deng, Songmin Kim, Navindra Navaratnam
  • Publication number: 20080231352
    Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Nasser A. Kurd, Chaodan Deng, Thomas P. Thomas
  • Publication number: 20070159215
    Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.
    Type: Application
    Filed: January 6, 2006
    Publication date: July 12, 2007
    Inventors: Chaodan Deng, Songmin Kim, Navindra Navaratnam