Abstract: Storage management techniques involve determining, from a set of users sharing a storage system, a plurality of target users with storage quotas to be updated; obtaining a total increase storage quota to be increased for the storage system; and determining allocation of the total increase storage quota among the plurality of target users according to at least one of a first strategy associated with quota proportions and a second strategy associated with a used storage capacity. The allocation of the increase storage quota is determined automatically according one or more predefined strategies, which can achieve storage quota allocation effectively and automatically, thereby increasing storage efficiency.

Abstract: Techniques for adjusting storage space involve: receiving a request for adjusting available storage space of a user in a filesystem from a first size to a second size; determining whether to allow to adjust the available storage space based on the request; and in response to allowing to adjust the available storage space, adjusting the available storage space to the second size. Accordingly, not only operations that an administrator needs to perform for adjusting the available storage space of a user is reduced, but also a quick and correct response for a request from a user of adjusting the available storage space is guaranteed.

Abstract: Techniques for accessing a file involve determining whether a client requests a permission for a target file, the permission allowing the client to cache data associated with the target file. The techniques further involve in response to determining that the client requests the permission, obtaining pattern information related to an access pattern in which the client accesses the target file. The techniques further involve determining availability of the permission to the client by applying the pattern information to a decision model, the decision model being trained based on training pattern information and training permission information. The techniques further involve providing, to the client, an indication on the availability. Accordingly, access conflicts can be reduced, so that the performance of the client and server can be improved.

Abstract: Techniques for shrinking a storage space involve determining a used storage space in a storage pool allocated to a plurality of file systems, and determining a usage level of a storage space in the storage pool based on the used storage space in and a storage capacity of the storage pool. The techniques further involve shrinking a storage space from one or more of the plurality of file systems based on the usage level of the storage pool. Such techniques may automatically shrink storage space in one or more file systems from the global level of the storage pool, which determines an auto shrink strategy according to overall performance of the storage pool, thereby improving efficiency of auto shrink and balancing system performance and saving space.

Abstract: An apparatus and a method are disclosed. In the apparatus, a memory management unit includes: a first cache unit, adapted to store a plurality of first source operands and one first write address; a second cache unit, adapted to store at least one pair of a second source operand and a second destination address; a write cache module, adapted to discriminate between destination addresses of a plurality of store instructions, so as to store, in the first cache unit, a plurality of source operands corresponding to consecutive destination addresses, and to store, in the second cache unit, non-consecutive destination addresses and source operands corresponding to the non-consecutive destination addresses, where the first write address is an initial address of the consecutive destination addresses; and a bus transmission module, adapted to transmit the plurality of first source operands and the first write address in the first cache unit to a memory through a bus in a write burst transmission mode.

Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.

Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

Abstract: The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.

Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Abstract: A method, computer program product, and computing system for receiving a request from a client device to access a file stored in a storage system configured to be communicatively coupled to a plurality of client devices. It may be determined whether to delegate the file to the requesting client device based upon, at least in part, a reinforcement learning model, thus defining a file delegation determination. An access pattern associated with the file may be monitored. The reinforcement learning model may be updated based upon, at least in part, the monitored access pattern associated with the file and the file delegation determination.

Abstract: Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority

Abstract: A display panel with enhanced waterproof ability is disclosed and includes a thin film transistor glass substrate, a color filter glass substrate, a frame sealing layer, and a liquid crystal layer. The color filter glass substrate is opposite to the thin film transistor glass substrate. The frame sealing layer and liquid crystal layer are disposed between the thin film transistor glass substrate and the color filter glass substrate. A planarization layer and a passivation layer are sequentially stacked on a surface of the thin film transistor glass substrate facing the frame sealing layer. An outer periphery of the planarization layer adjacent to the narrow bezel display panel is defined with a waterproof groove. The passivation layer extends to a portion adjacent to the waterproof groove without extending into the waterproof groove. Outer peripheries of the passivation layer and the display panel are at an interval to improve waterproof ability.