Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput.

Abstract: A technique for segmented frame synchronization for Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) and Integrated Services Digital Broadcasting-Terrestrial Sound Broadcasting (ISDB-TSB) systems, wherein the method comprises receiving a wireless digital signal comprising an Orthogonal Frequency Division Multiplexing (OFDM) frame, further comprising ODFM symbols, in a receiver and wherein the receiver comprises a time de-interleaver, a bit de-interleaver, and a descrambler; filling memory of time de-interleaver and bit de-interleaver by the received wireless digital signal; determining an OFDM segmented frame boundary when memory of the time de-interleaver and bit de-interleaver are full; decoding bits from time de-interleaver and bit de-interleaver using a Viterbi decoder; outputting the Viterbi decoding bits from time de-interleaver and bit de-interleaver when the OFDM segmented frame boundary is detected; obtaining a segmented multiplexing frame boundary upon receipt of the first bit from the

Abstract: A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.

Abstract: Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; and reducing a re-acquisition time at every stage of the data bit re-synchronization sequence, wherein the reducing process results in a reduction in the time to perform the re-synchronization for the DVB-H receiver, wherein the reduction in the time to perform the re-synchronization for the DVB-H receiver is greater than one-half of the time required to perform the re-synchronization for the DVB-H receiver absent the reducing of the re-acquisition time at every stage of the data bit re-synchronization sequence.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein the method comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; removing an on-chip timer and internal state registers in the DVB-H receiver; and allowing the DVB-H receiver to power off in between receipt of data bursts. Preferably, the removing process reduces the time to perform the re-synchronization in the DVB-H receiver. Preferably, the data bit re-synchronization sequence comprises performing an automatic gain control (AGC) lock process; performing a mode and guard detecting process; performing a frequency offset estimation process; performing a transmit parameter signaling (TPS) detection process; performing a timing and carrier loop lock process; and performing an equalizer delay process.

Abstract: A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput.

Abstract: A technique for segmented frame synchronization for Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) and Integrated Services Digital Broadcasting-Terrestrial Sound Broadcasting (ISDB-TSB) systems, wherein the method comprises receiving a wireless digital signal comprising an Orthogonal Frequency Division Multiplexing (OFDM) frame, further comprising ODFM symbols, in a receiver and wherein the receiver comprises a time de-interleaver, a bit de-interleaver, and a descrambler; filling memory of time de-interleaver and bit de-interleaver by the received wireless digital signal; determining an OFDM segmented frame boundary when memory of the time de-interleaver and bit de-interleaver are full; decoding bits from time de-interleaver and bit de-interleaver using a Viterbi decoder; outputting the Viterbi decoding bits from time de-interleaver and bit de-interleaver when the OFDM segmented frame boundary is detected; obtaining a segmented multiplexing frame boundary upon receipt of the first bit from the

Abstract: Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

Abstract: A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; and reducing a re-acquisition time at every stage of the data bit re-synchronization sequence, wherein the reducing process results in a reduction in the time to perform the re-synchronization for the DVB-H receiver, wherein the reduction in the time to perform the re-synchronization for the DVB-H receiver is greater than one-half of the time required to perform the re-synchronization for the DVB-H receiver absent the reducing of the re-acquisition time at every stage of the data bit re-synchronization sequence.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein the method comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; removing an on-chip timer and internal state registers in the DVB-H receiver; and allowing the DVB-H receiver to power off in between receipt of data bursts. Preferably, the removing process reduces the time to perform the re-synchronization in the DVB-H receiver. Preferably, the data bit re-synchronization sequence comprises performing an automatic gain control (AGC) lock process; performing a model and guard detecting process; performing a frequency offset estimation process; performing a transmit parameter signaling (TPS) detection process; performing a timing and carrier loop lock process; and performing an equalizer delay process.