Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A product order prediction method adapts to a production planning system. The method comprises obtaining a reference data related to a next reference order and a current actual order, performing an algorithm based on the neural network model according to the reference data and the current actual order to generate a feature vector, and performing another algorithm based on the neural network model according to the feature vector to output a next predicted order to the production planning system, for the production planning system to generate an operation plan of a production line of the product according to the next predicted order.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: The present invention provides a slit-scan multi-wavelength confocal lens module, utilizing at least two lenses having chromatic aberration for splitting a broadband light into continuously linear spectral lights having different focal length respectively. The present invention utilizes the confocal lens module employing slit-scan confocal principle and chromatic dispersion techniques and the confocal microscopy with optical sectioning ability and high resolution in spectral dispersion to establish a confocal microscopy method and system with long DOF and high resolution, capable of modulating a broadband light to produce the axial chromatic dispersion and focus on different depths toward an object's surface for obtaining the reflected light spectrum from the surface.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: A method of error checking and correction includes: performing compression upon an original data packet and generating a compressed data packet; determining an error correcting code length according to a data length; generating an error correcting code by performing error checking and correction encoding upon a packet data according to the error correcting code length; and combining the packet data and error correcting code into an encoded data packet. A method of error checking and correction includes: reading an encoded data packet, wherein the encoded data packet includes a packet data and an error correcting code, and the packet data includes a compressed data packet; generating a decoded compressed data packet corresponding to the compressed data packet by performing error checking and correction decoding upon the packet data according to the error correcting code; and performing decompression upon the decoded compressed data packet to generate a decompressed data packet.

Abstract: A method for fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate. A metal oxide material layer is formed on the gate insulating layer. A photoresist layer is formed on the metal oxide material layer, in which a thickness of the photoresist layer above the gate is larger than that of the photoresist layer above two sides adjacent to the gate. A portion of the metal oxide material layer is removed to form a metal oxide active layer by using the photoresist layer as a mask. The photoresist layer above the two sides adjacent to the gate is removed and the remaining photoresist layer covers a portion of the metal oxide active layer. A source and a drain are formed on the metal oxide active layer covered by the photoresist layer.

Abstract: An access method of a volatile memory accesses the volatile memory via a block access fashion. The volatile memory includes a plurality of blocks. The method includes: performing a reading operation for a block having at least one known bad cell among the blocks, which includes reading a block data and an error correction code data corresponding to the block and applying the ECC data to correct data read from the at least one known bad cell to generate a corrected block data.