Patents by Inventor Chao-Nan Chen
Chao-Nan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240304705Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: ApplicationFiled: May 16, 2024Publication date: September 12, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 12021134Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: GrantFiled: December 1, 2022Date of Patent: June 25, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20230369460Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.Type: ApplicationFiled: June 9, 2022Publication date: November 16, 2023Applicant: United Microelectronics Corp.Inventors: Kuang-Hsiu Chen, Wei-Chung Sun, Chao Nan Chen, Chun-Wei Yu, Kuan Hsuan Ku, Shao-Wei Wang
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Publication number: 20230097129Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: ApplicationFiled: December 1, 2022Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 11545560Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: GrantFiled: January 28, 2021Date of Patent: January 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20210151580Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20210073896Abstract: A product order prediction method adapts to a production planning system. The method comprises obtaining a reference data related to a next reference order and a current actual order, performing an algorithm based on the neural network model according to the reference data and the current actual order to generate a feature vector, and performing another algorithm based on the neural network model according to the feature vector to output a next predicted order to the production planning system, for the production planning system to generate an operation plan of a production line of the product according to the next predicted order.Type: ApplicationFiled: December 18, 2019Publication date: March 11, 2021Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Jonathan Hans SOESENO, Trista Pei-Chun CHEN, Chih Hung HUANG, Junh Hsien TU, Wei-Chao CHEN, Chao-Nan CHEN
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Patent number: 10943991Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.Type: GrantFiled: March 6, 2019Date of Patent: March 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20200243664Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.Type: ApplicationFiled: March 6, 2019Publication date: July 30, 2020Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 10700202Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.Type: GrantFiled: October 28, 2018Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20200098916Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.Type: ApplicationFiled: October 28, 2018Publication date: March 26, 2020Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20180269107Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.Type: ApplicationFiled: March 14, 2017Publication date: September 20, 2018Inventors: Yat-Kai Sun, Chao-Nan Chen, Hung-Lin Shih, Che-Hung Huang, Wei-Lun Hsu, Cheng-Chia Liu
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Patent number: 10079180Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.Type: GrantFiled: March 14, 2017Date of Patent: September 18, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yat-Kai Sun, Chao-Nan Chen, Hung-Lin Shih, Che-Hung Huang, Wei-Lun Hsu, Cheng-Chia Liu
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Patent number: 9164777Abstract: Technologies are described herein for determining the display of equal spacing guides between diagram shapes. The nearest neighbors of each shape in a diagram are determined, and the distances between each shape and its nearest neighbors are calculated. When an active shape in the diagram is positioned or moved, spacing guides are displayed between shapes having equidistant spacing when the calculated distances between shapes become equal to a distance between the active shape and one of its nearest neighbors.Type: GrantFiled: August 30, 2011Date of Patent: October 20, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Ankit Prasad, Jeffrey Chao-Nan Chen, Onur Onder
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Patent number: 9059745Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.Type: GrantFiled: March 10, 2013Date of Patent: June 16, 2015Assignee: JMicron Technology Corp.Inventors: Kuo-Hua Yuan, Chao-Nan Chen
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Patent number: 8836706Abstract: A request may be received to trigger an animation action in response to reaching a bookmark during playback of a media object. In response to the request, data is stored defining a new animation timeline configured to perform the animation action when playback of the media object reaches the bookmark. When the media object is played back, a determination is made as to whether the bookmark has been encountered. If the bookmark is encountered, the new animation timeline is started, thereby triggering the specified animation action. An animation action may also be added to an animation timeline that triggers a media object action at a location within a media object. When the animation action is encountered during playback of the animation timeline, the specified media object action is performed on the associated media object.Type: GrantFiled: December 18, 2008Date of Patent: September 16, 2014Assignee: Microsoft CorporationInventors: Jason Xiaobo Zhao, Jeffrey Chao-Nan Chen, Barn-Wan Li, Runzhen Huang
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Patent number: 8773757Abstract: The present invention provides a slit-scan multi-wavelength confocal lens module, utilizing at least two lenses having chromatic aberration for splitting a broadband light into continuously linear spectral lights having different focal length respectively. The present invention utilizes the confocal lens module employing slit-scan confocal principle and chromatic dispersion techniques and the confocal microscopy with optical sectioning ability and high resolution in spectral dispersion to establish a confocal microscopy method and system with long DOF and high resolution, capable of modulating a broadband light to produce the axial chromatic dispersion and focus on different depths toward an object's surface for obtaining the reflected light spectrum from the surface.Type: GrantFiled: January 22, 2010Date of Patent: July 8, 2014Assignee: National Taipei University of TechnologyInventors: Liang-Chia Chen, Chao-Nan Chen, Yi-Wei Chang
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Publication number: 20140129897Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.Type: ApplicationFiled: March 10, 2013Publication date: May 8, 2014Applicant: JMicron Technology Corp.Inventors: Kuo-Hua Yuan, Chao-Nan Chen
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Publication number: 20140122964Abstract: A method of error checking and correction includes: performing compression upon an original data packet and generating a compressed data packet; determining an error correcting code length according to a data length; generating an error correcting code by performing error checking and correction encoding upon a packet data according to the error correcting code length; and combining the packet data and error correcting code into an encoded data packet. A method of error checking and correction includes: reading an encoded data packet, wherein the encoded data packet includes a packet data and an error correcting code, and the packet data includes a compressed data packet; generating a decoded compressed data packet corresponding to the compressed data packet by performing error checking and correction decoding upon the packet data according to the error correcting code; and performing decompression upon the decoded compressed data packet to generate a decompressed data packet.Type: ApplicationFiled: March 13, 2013Publication date: May 1, 2014Applicant: JMicron Technology Corp.Inventor: Chao-Nan Chen
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Patent number: 8578259Abstract: Tools and techniques for media portability and compatibility for different destination platforms are provided. These tools may receive commands to launch a media portability capability, and may receive source media as input for transformation. These tools may also receive indications of profile settings for specifying how to transform the source media for enhanced portability on destination systems for playback. The source media may be transformed in response to the profile setting, with the transformed media inserted into a document. The tools may then distribute the document to the destination system for playback.Type: GrantFiled: December 31, 2008Date of Patent: November 5, 2013Assignee: Microsoft CorporationInventors: Jeffrey Chao-Nan Chen, Barn-Wan Li, Kai Chung Lui