Abstract: A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.

Abstract: Fan-out wafer-level packaging (FOWLP) integrated circuits (ICs) employing electro-magnetic (EM) interference (EMI) shield structure in fan out area for EMI shielding, and related fabricating methods are disclosed. The IC includes a semiconductor die (“IC die”) that is bonded to the reconstituted carrier wafer such that a fan-out area is provided between adjacent IC dies to provide area for fan-out interconnects to provide additional die interconnections to the IC die. In exemplary aspects, the IC includes an EMI shield that includes vias formed in an un-used area in fan-out area adjacent to the IC die electrically that are otherwise unused for input/output (I/O) signal interconnects for coupling I/O signals to the IC die. The EMI shield is electrically coupled to a ground node of the IC die to provide an effective EMI shield to block or attenuate unwanted EM noise propagated from the IC die outside the IC.

Abstract: A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

Abstract: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.

Abstract: Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.

Abstract: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.

Abstract: The disclosed embodiments relate to an optoelectronic module, comprising one or more optical chips, and a molded substrate, which is molded around the one or more optical chips, so that the one or more optical chips are embedded in the molded substrate, and an active surface of each optical chip remains exposed. This molded substrate includes one or more through vias that provide electrical signal paths through the molded substrate. After the molded substrate is fabricated, one or more integrated circuit (IC) chips can be flip-mounted to the molded substrate and electrically connected to the one or more embedded optical chips and the one or more through vias. Also, one or more optical connectors containing optical waveguides can be flip-mounted on the molded substrate and optically coupled to the one or more embedded optical chips.

Abstract: The disclosed embodiments relate to a system for assembling an optical connector. During the assembly process, the system first fabricates the optical connector, wherein the optical connector is precut and includes a fiber coupler for connecting to an external optical fiber. Next, the system bonds the optical connector to a photonic chip, wherein the photonic chip includes an optical coupler, which is coupled to one or more optical components within the photonic chip. Finally, after the optical connector is bonded to the photonic chip, the system uses a laser to write a coupling waveguide in the optical connector, wherein the coupling waveguide is routed through the optical connector to connect the optical coupler in the photonic chip with the fiber coupler for connecting to the external optical fiber.

Abstract: Described herein are cell culture interfaces that can be configured to relay an energy between a cell and an electronic interface and methods of using the cell culture interfaces that can be configured to relay an energy between a cell and an electronic interface.

Abstract: During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism.

Abstract: During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.