Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a first movable assembly and a first driving assembly. The first movable assembly is configured to connect a first optical element, and the first movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the first movable assembly to move relative to the fixed assembly in a first dimension.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a first movable assembly and a first driving assembly. The first movable assembly is configured to connect a first optical element, and the first movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the first movable assembly to move relative to the fixed assembly in a first dimension.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.

Abstract: An image processing chip and an image processing system are provided. The image processing chip includes a first image end, a second image end, an image processing block and a multiplexer. The first image end receives at least one first image data packet. The image processing block is used to convert the at least one first image data packet into at least one second image data packet. The multiplexer has a first input end coupled to the first image end, a second input end coupled to the image processing block, and an output end coupled to the second image end. When the image processing chip operates in a first mode, the multiplexer is coupled to the first input end and the output end to transmit the at least one first image data packet from the first image end to the second image through the multiplexer.

Abstract: An image processing chip and an image processing system are provided. The image processing chip includes a first image end, a second image end, an image processing block and a multiplexer. The first image end receives at least one first image data packet. The image processing block is used to convert the at least one first image data packet into at least one second image data packet. The multiplexer has a first input end coupled to the first image end, a second input end coupled to the image processing block, and an output end coupled to the second image end. When the image processing chip operates in a first mode, the multiplexer is coupled to the first input end and the output end to transmit the at least one first image data packet from the first image end to the second image through the multiplexer.

Abstract: The invention provides a method of managing SDIO commands at a host device and a peripheral device. The host device connected to the peripheral device by a bus comprising a command transmission line and a data transmission line, both of which are arranged to transmit single end signal. The host device converts operation requests into converted commands and combines a first SDIO complied data packet with the converted commands to generate a first combined data packet. Then, the host device transmits the first combined data packet through the data transmission line, wherein the first combined data packet comprises a first header for indicating whether the first combined data packet comprises the converted commands. After receiving the first combined data packet, the peripheral device parses the first combined data packet to obtain the converted commands, and then performs processing procedures according to the converted commands.

Abstract: The invention provides a method of managing SDIO commands at a host device and a peripheral device. The host device connected to the peripheral device by a bus comprising a command transmission line and a data transmission line, both of which are arranged to transmit single end signal. The host device converts operation requests into converted commands and combines a first SDIO complied data packet with the converted commands to generate a first combined data packet. Then, the host device transmits the first combined data packet through the data transmission line, wherein the first combined data packet comprises a first header for indicating whether the first combined data packet comprises the converted commands. After receiving the first combined data packet, the peripheral device parses the first combined data packet to obtain the converted commands, and then performs processing procedures according to the converted commands.

Abstract: A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.

Abstract: A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.

Abstract: The invention provides a method of managing SDIO commands. Firstly, before a first packet complying with a first SDIO data format is transmitted, an operation request is converted into a converted command. The operation request is originally set to be converted into a command complying with a SDIO command format. Then, the fist packet and the converted command are combined to generate a first combined packet. Afterward, the first combined packet is transmitted. After the first combined packet is received, the first combined packet is parsed to obtain the converted command. Finally, a processing procedure is performed according to the converted command.

Abstract: The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.

Abstract: The present invention relates to a programmable frequency divider, comprising one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.