Patents by Inventor Char-Ming Huang

Char-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reference voltage generator with op-amp buffer
    Patent number: 9304528
    Abstract: A reference voltage circuit and method making same, the reference voltage circuit including: a first sub-circuit for generating first and second temperature-compensated voltages; a second sub-circuit configured to receive the first and second temperature-compensated voltages and generate first and second reference voltages based on the first and second temperature-compensated voltages, respectively; and a third sub-circuit configured to receive and change voltage levels of the first and second reference voltages, and output a third reference voltage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Char-Ming Huang
  • Method of reducing parasitic mismatch
    Patent number: 8850374
    Abstract: A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Char-Ming Huang, Hui-Yu Lee
  • REFERENCE VOLTAGE CIRCUIT
    Publication number: 20140152290
    Abstract: A reference voltage circuit and method making same, the reference voltage circuit including: a first sub-circuit for generating first and second temperature-compensated voltages; a second sub-circuit configured to receive the first and second temperature-compensated voltages and generate first and second reference voltages based on the first and second temperature-compensated voltages, respectively; and a third sub-circuit configured to receive and change voltage levels of the first and second reference voltages, and output a third reference voltage.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Char-Ming Huang
  • Method of Reducing Parasitic Mismatch
    Publication number: 20140130001
    Abstract: A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Char-Ming Huang, Hui-Yu Lee