Patents by Inventor Charaf-Eddine Souria

Charaf-Eddine Souria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230108806
    Abstract: A method for radar detection of targets includes: determining digital data representative of the radar environment in real time, calculating a probability of existence of mock targets in a plurality of regions of the radar environment on the basis of the digital data representative of the radar environment, receiving digital data corresponding to at least one radar target, transmitted by the radar, including digital location data of the at least one radar target, calculating a reliable confidence index associated with the at least one radar target according to the probability of existence of mock targets in the region where the at least one radar target is located.
    Type: Application
    Filed: February 4, 2021
    Publication date: April 6, 2023
    Applicant: RENAULT S.A.S
    Inventor: Charaf-Eddine SOURIA
  • Patent number: 10498299
    Abstract: A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Charaf Eddine Souria, Cristian Pavao Moreira
  • Publication number: 20180123536
    Abstract: A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 3, 2018
    Inventors: Charaf Eddine Souria, Cristian Pavao Moreira
  • Patent number: 9711471
    Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: July 18, 2017
    Assignee: NXP USA, Inc.
    Inventors: Charaf-Eddine Souria, Gilles Montoriol, Stéphane Damien Thuries
  • Publication number: 20170141057
    Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
    Type: Application
    Filed: April 18, 2016
    Publication date: May 18, 2017
    Inventors: Charaf-Eddine Souria, Gilles Montoriol, Stéphane Damien Thuries