Patents by Inventor Charan Enugala

Charan Enugala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Retimer with host-interactive data logging engine
    Patent number: 11941436
    Abstract: An integrated-circuit retimer selectively logs information corresponding to mission-mode data, received and transmitted via counterpart high-bandwidth data interfaces, in real-time and accordance with contents of a logging control storage written by an external component during retimer run time.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: March 26, 2024
    Assignee: Astera Labs, Inc.
    Inventors: Ken (Keqin) Han, Casey Morrison, Charan Enugala, Pulkit Khandelwal, Vikas Khandelwal
  • Low-latency retimer with seamless clock switchover
    Patent number: 11853115
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: December 26, 2023
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Low-latency retimer with seamless clock switchover
    Patent number: 11487317
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 1, 2022
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Configurable-aggregation retimer with media-dedicated controllers
    Patent number: 11327913
    Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Astera Labs, Inc.
    Inventors: Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Vivek Trivedi
  • Low-latency signaling-link retimer
    Patent number: 11258696
    Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: February 22, 2022
    Assignee: Asiera Labs, Inc.
    Inventors: Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Ken (Keqin) Han, Charan Enugala, Vivek Trivedi, Chi Feng
  • Low-latency retimer with seamless clock switchover
    Patent number: 11150687
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi