Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.

Abstract: A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of iterations, each iteration includes attempting to set the target analog values and then verifying whether the target analog values have been reached in accordance with a verification condition. After applying a predefined number of the iterations, the verification condition is relaxed and a condition of whether the target analog values have been reached in accordance with the relaxed verification condition is verified.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.

Abstract: Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method may include applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method may further include determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract: The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not radiation sensitive. The radiation sensitive compound also includes a body portion disposed between the surface binding group and the metal binding group, and a radiation sensitive group positioned in the body portion or adjacent to the metal binding group. The surface binding group is capable of attaching to a substrate selected from a metal, a metal oxide, or a semiconductor material.

Abstract: The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not radiation sensitive. The radiation sensitive compound also includes a body portion disposed between the surface binding group and the metal binding group, and a radiation sensitive group positioned in the body portion or adjacent to the metal binding group. The surface binding group is capable of attaching to a substrate selected from a metal, a metal oxide, or a semiconductor material.

Abstract: The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not radiation sensitive. The radiation sensitive compound also includes a body portion disposed between the surface binding group and the metal binding group, and a radiation sensitive group positioned in the body portion or adjacent to the metal binding group. The surface binding group is capable of attaching to a substrate selected from a metal, a metal oxide, or a semiconductor material.

Abstract: The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not radiation sensitive. The radiation sensitive compound also includes a body portion disposed between the surface binding group and the metal binding group, and a radiation sensitive group positioned in the body portion or adjacent to the metal binding group. The surface binding group is capable of attaching to a substrate selected from a metal, a metal oxide, or a semiconductor material.