Patents by Inventor Charan Veera Venkata Satya Surisetty
Charan Veera Venkata Satya Surisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559654Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.Type: GrantFiled: November 29, 2017Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 10249624Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.Type: GrantFiled: September 7, 2017Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Patent number: 9966374Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.Type: GrantFiled: April 12, 2016Date of Patent: May 8, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan Veera Venkata Satya Surisetty
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Publication number: 20180090566Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.Type: ApplicationFiled: November 29, 2017Publication date: March 29, 2018Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 9905421Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.Type: GrantFiled: July 28, 2016Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 9871099Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.Type: GrantFiled: November 9, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Publication number: 20180012892Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.Type: ApplicationFiled: September 7, 2017Publication date: January 11, 2018Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Patent number: 9768173Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.Type: GrantFiled: July 26, 2016Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Patent number: 9685340Abstract: After forming a first contact opening to expose a portion of a first source/drain contact located at one side of a functional gate structure followed by forming a second contact opening that intersects the first contact opening to expose the functional gate structure and a portion of a second source/drain contact located at an opposite side of the functional gate structure, the exposed portions of the first source/drain contact and the second-side source/drain contact are recessed. A dielectric cap is subsequently formed over the recessed portion of the second source/drain contact. A shared contact is formed in the first contact opening and the second contact opening to electrically connect a gate conductor of the functional gate structure to the first source/drain contact. The dielectric cap isolates the second source/drain contact from the shared contact, thus preventing contact shorts in a one-sided gate tie-down structure for 7 nm node and beyond.Type: GrantFiled: June 29, 2015Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Publication number: 20170154774Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.Type: ApplicationFiled: July 28, 2016Publication date: June 1, 2017Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty
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Publication number: 20170133459Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.Type: ApplicationFiled: November 9, 2015Publication date: May 11, 2017Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 9595592Abstract: A method for forming contact silicide for a semiconductor structure. In one embodiment, a dielectric layer is formed over a p-type region of a semiconductor structure comprising a gate stack and source and drain regions. The source and drain regions are formed within a semiconductor layer. First and second contact trenches are formed within the dielectric layer exposing at least a portion of the source region and a portion of the drain region, respectively. First and second metal layers are formed within the first and second contact trenches. The second metal layer includes a metallic material that is different from a metallic material of the first meal layer. The metallic materials of the first and second metal layers in a lower region of the first and second contact trenches are intermixed. A silicide is formed within the source and drain regions from the semiconductor layer and the intermixed metallic materials.Type: GrantFiled: December 30, 2015Date of Patent: March 14, 2017Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Publication number: 20160379925Abstract: After forming a first contact opening to expose a portion of a first source/drain contact located at one side of a functional gate structure followed by forming a second contact opening that intersects the first contact opening to expose the functional gate structure and a portion of a second source/drain contact located at an opposite side of the functional gate structure, the exposed portions of the first source/drain contact and the second-side source/drain contact are recessed. A dielectric cap is subsequently formed over the recessed portion of the second source/drain contact. A shared contact is formed in the first contact opening and the second contact opening to electrically connect a gate conductor of the functional gate structure to the first source/drain contact. The dielectric cap isolates the second source/drain contact from the shared contact, thus preventing contact shorts in a one-sided gate tie-down structure for 7 nm node and beyond.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 9508816Abstract: A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure. Each sacrificial gate structure is then removed forming gate cavities. A high k dielectric material, a metal nitride hard mask and a physical vapor deposited (PVD) amorphous-silicon cap are provided. Vertical portions of the metal nitride hard mask and the high k dielectric material are removed from a portion of each gate cavity. Additional PVD amorphous silicon is then deposited and then all amorphous silicon and remaining metal nitride hard mask portions are removed. A work function portion having a stair-like surface, a diffusion barrier portion, a conductive metal structure and a dielectric cap are then formed into to each of the gate cavities.Type: GrantFiled: February 12, 2016Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Publication number: 20160336323Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Patent number: 9484401Abstract: After forming source/drain contact trenches to expose source/drain regions, contact liner material layer portions are formed on sidewalls and bottom surfaces of the source/drain contact trenches. Contact material layer portions are then formed over the contact liner material layer portions to fill in the source/drain contact trenches. At least portions of the contact material layer portions and the contact liner material layer portions present on sidewalls of the source/drain contact trenches are removed to provide source/drain contacts with reduced contact capacitance.Type: GrantFiled: November 24, 2014Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
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Patent number: 9461168Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.Type: GrantFiled: February 18, 2016Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty
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Patent number: 9431486Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.Type: GrantFiled: November 30, 2015Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty
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Publication number: 20160225766Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.Type: ApplicationFiled: April 12, 2016Publication date: August 4, 2016Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan Veera Venkata Satya Surisetty
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Patent number: 9406568Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.Type: GrantFiled: November 21, 2014Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty