Patents by Inventor Charavana Gurumurthy

Charavana Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of enabling solder deposition on a substrate and electronic package formed thereby
    Patent number: 7825022
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Charavana Gurumurthy
  • Method of enabling solder deposition on a substrate and electronic package formed thereby
    Publication number: 20090277866
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 12, 2009
    Inventors: RAVI NALLA, CHARAVANA GURUMURTHY
  • Method of enabling solder deposition on a substrate and electronic package formed thereby
    Patent number: 7538429
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Charavana Gurumurthy
  • Method of enabling solder deposition on a substrate and electronic package formed thereby
    Publication number: 20080042248
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Inventors: Ravi Nalla, Charavana Gurumurthy
  • Method of providing solder bumps of mixed sizes on a substrate using solder transfer in two stages
    Publication number: 20080003804
    Abstract: A method of providing solder bumps on electrode pads of a microelectronic substrate. The method includes: disposing starter solder portions onto respective ones of the electrode pads; performing a starter reflow comprising reflowing the starter solder portions to form starter solder bumps on respective ones of the electrode pads; disposing respective filler solder portions onto respective ones of the starter solder bumps; and performing a filler reflow comprising reflowing the filler solder portions on respective ones of the starter solder bumps to yield respective final solder bumps on the electrode pads.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Ravi Nalla, Mengzhi Pang, Charavana Gurumurthy
  • Method of substrate manufacture that decreases the package resistance
    Publication number: 20070148971
    Abstract: A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold. An apparatus includes a package substrate including a plurality of land contacts wherein each of the plurality of land contacts includes a coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Bijay Saha, Munehiro Toyama, Ehab Nasir, Omar Bchir, Charavana Gurumurthy