Patents by Inventor Charavana K. Gurumurthy
Charavana K. Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10317952Abstract: An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s), extending outwardly from the rectangular opening, wherein each of the slots comprises: an inner opening having a length coextensive with a side of the rectangular opening, and an outer opening having corresponding ends that extend a length of the outer opening beyond the length of the inner opening. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 30, 2016Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Sandeep S. Iyer, Amanuel Abebaw, Mark Saltas, Mayank Patel, Charavana K. Gurumurthy, Suriyakala Ramalingam, Vladimir Malamud
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Patent number: 10103037Abstract: Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant.Type: GrantFiled: May 9, 2014Date of Patent: October 16, 2018Assignee: Intel CorporationInventors: Aleksandar Aleksov, Dilan Seneviratne, Charavana K. Gurumurthy, Ching-Ping J. Shen, Daniel N. Sobieski
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Publication number: 20180095503Abstract: An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s), extending outwardly from the rectangular opening, wherein each of the slots comprises: an inner opening having a length coextensive with a side of the rectangular opening, and an outer opening having corresponding ends that extend a length of the outer opening beyond the length of the inner opening. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Sandeep S. IYER, Amanuel ABEBAW, Mark SALTAS, Mayank PATEL, Charavana K. GURUMURTHY, Suriyakala RAMALINGAM, Vladimir MALAMUD
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Patent number: 9691727Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.Type: GrantFiled: April 14, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Javier Soto Gonzalez, Charavana K. Gurumurthy, Robert M. Nickerson, Debendra Mallik
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Patent number: 9299602Abstract: A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process.Type: GrantFiled: December 20, 2011Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Qinglei Zhang, Tao Wu, Mark S. Hlad, Charavana K. Gurumurthy
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Patent number: 9190315Abstract: A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process.Type: GrantFiled: December 20, 2011Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Qinglei Zhang, Tao Wu, Mark S. Hlad, Charavana K. Gurumurthy
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Publication number: 20150325491Abstract: Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Inventors: Aleksandar Aleksov, Dilan Seneviratne, Charavana K. Gurumurthy, Ching-Ping J. Shen, Daniel N. Sobieski
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Publication number: 20150221608Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.Type: ApplicationFiled: April 14, 2015Publication date: August 6, 2015Applicant: Intel CorporationInventors: Javier SOTO GONZALEZ, Charavana K. GURUMURTHY, Robert M. NICKERSON, Debendra MALLIK
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Publication number: 20130320547Abstract: A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process.Type: ApplicationFiled: December 20, 2011Publication date: December 5, 2013Inventors: Qinglei Zhang, Tao Wu, Mark S. Hlad, Charavana K. Gurumurthy
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Patent number: 8450857Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.Type: GrantFiled: June 18, 2012Date of Patent: May 28, 2013Assignee: Intel CorporationInventors: Mihir K. Roy, Islam A. Salama, Charavana K. Gurumurthy, Robert L. Sankman
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Publication number: 20120299179Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.Type: ApplicationFiled: June 18, 2012Publication date: November 29, 2012Inventors: Mihir K. Roy, Islam A. Salama, Charavana K. Gurumurthy, Robert L. Sankman
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Patent number: 8278214Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.Type: GrantFiled: December 23, 2009Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Mihir K. Roy, Islam A. Salama, Charavana K. Gurumurthy, Robert L. Sankman
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Publication number: 20110147929Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Mihir K. Roy, Islam A. Salama, Charavana K. Gurumurthy, Robert L. Sankman
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Patent number: 7432202Abstract: A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold. An apparatus includes a package substrate including a plurality of land contacts wherein each of the plurality of land contacts includes a coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold.Type: GrantFiled: December 28, 2005Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Bijay S. Saha, Munehiro Toyama, Ehab A. Nasir, Omar J. Bchir, Charavana K. Gurumurthy