Abstract: The structure and process for packaging multi-chip, which includes: a substrate; a plurality of chips, locating above said substrate and each chip is conducted electrically with the substrate by wire-bonding; several adhesion layers, each locating between any two adjacent chips to make themselves as a sandwiched shape; and several spacers, each covered in each of the adhesion layers for supporting each of the chips. Wherein, there is no suspension zone between each chip for facilitating the control of the wire-binding and making wire-bonding more accurately for raising the yield of process effectively.