Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In one embodiment, a processing node can be comprised of modular processing elements to perform computations associated with an extended instruction. Also, such a node includes at least two multifunctional memories and a data flow director configured to selectably couple the first multifunctional memory and the second multifunctional memory. The data flow director is configured to route data out from a first multifunctional memory of the two multifunctional memories while data is being routed into a second multifunctional memory. In another embodiment, a processing node is configured to compute a function output based on a number of Boolean functions, wherein at least one of the multifunctional memories is configured as a look-up table (“LUT”).

Abstract: The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of an array of other similar circuits to form, for example, a larger multiplier.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: A programmable logic core (PLC) can be integrated into custom ICs such as ASICs and SOCs using a unique design methodology. For example, the methodology can incorporate the PLC into the entire ASIC design process from chip level RTL to final tape-out and resolve issues ranging from RTL guidelines through to sub-micron signal integrity. The post-manufacture programming flow is considered up-front during the ASIC flow and tools ensure successful programming in the field environment for the lifetime of the product. An example PLC architecture for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs and is implemented as a hard macro, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry and is included in the same hard macro, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces that is implemented as a soft-macro.

Abstract: The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of an array of other similar circuits to form, for example, a larger multiplier.

Abstract: A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: Carry lookahead techniques are adapted for implementation in a programmable logic device. In one example of the invention, a carry result is computed for a block of function cells, each function cell representing one bit in a multibit operation that uses carry. This carry result is combined with the carry input from a function cell block representing less significant bits in the operation and a carry output is provided to a function cell block representing more significant bits in the operation. The received carry can also be supplied to adjust provisional carry results for each bit associated with the function cells in the block. Accordingly, the received carry input need not be rippled through all the function cells in the block, thus reducing carry propagation delays.

Abstract: An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units.

Abstract: A bus transceiver system transfers data among a plurality (N) of system components. The system includes N toggle bus transceiver circuits (TBT.sub.i, for i=0 through N-1), each of which corresponds to a respective one of the system components. Each toggle bus transceiver circuit has bi-directional driver circuitry which has M first terminals (D.sub.i,j, for j=0 through M-1). Each of the M first terminals are coupled to a respective bit of the system component to which that toggle bus transceiver circuit corresponds. Each toggle bus tranceiver circuit further has M second terminals (P.sub.i,j). Driver switch circuitry of each toggle bus transceiver circuit selectively connects each of the M first terminals to at least one of said M second terminals. In a first mode, the driver circuitry drives in a first direction and in a second mode, the driver circuitry drives in a second direction. Repeater of each toggle bus transceiver circuit has M third terminals (Q.sub.i,j) and M latch circuits (L.sub.i,j).

Abstract: An information processing system employing functionally distributed multiple processors has a unique manner of interconnecting and controlling the processors so that the deadlock problem is avoided even though the interconnection of the processors is based on a graph basis in the mathematical sense. The system employs a plurality of control processors of the same or different design to control by sequences of instructions the operation of data processors or other control processors. Each data processor performs a specific set of functions on varying data structures to accomplish such purposes as providing a memory in which a program resides or performs arithmetic or string computations. The design of the control and data processors are required to meet the definition of a control arc scheme for inter-processor communication.