Abstract: The present disclosure generally relates to a system and method for providing an action-based donation platform. An exemplary electronic device displays a plurality of graphical representations corresponding to a plurality of activities and displays a first graphical representation corresponding to a contribution goal. The electronic device receives a user input specifying an activity and a contribution amount corresponding to an instance of the activity. Based on the user input, the electronic device adds a second graphical representation corresponding to the specified activity to the plurality of graphical representations. The electronic device receives a user selection of the second graphical representation, and in response to receiving the user selection of the second graphical representation, displays an indication of a contribution corresponding to the contribution goal.

Abstract: The present disclosure generally relates to a system and method for providing an action-based donation platform. An exemplary electronic device displays a plurality of graphical representations corresponding to a plurality of activities and displays a first graphical representation corresponding to a contribution goal. The electronic device receives a user input specifying an activity and a contribution amount corresponding to an instance of the activity. Based on the user input, the electronic device adds a second graphical representation corresponding to the specified activity to the plurality of graphical representations. The electronic device receives a user selection of the second graphical representation, and in response to receiving the user selection of the second graphical representation, displays an indication of a contribution corresponding to the contribution goal.

Abstract: Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.

Abstract: The present invention in one or more embodiments provides a compartment panel assembly to be positioned between one or more seats and a trunk storage of a vehicle. The compartment panel includes a panel portion, a protruding portion extending from the panel portion and including a first wall which defines thereupon a first aperture, and a first storage container to be at least partially received through the first aperture. The present invention in one or more embodiments is advantageous positioned in providing effective storage within the vehicle interior, and in particular providing storage spaces that are lockable and/or not directly visible for enhanced storage security.

Abstract: The present invention in one or more embodiments provides a compartment panel assembly to be positioned between one or more seats and a trunk storage of a vehicle. The compartment panel includes a panel portion, a protruding portion extending from the panel portion and including a first wall which defines thereupon a first aperture, and a first storage container to be at least partially received through the first aperture. The present invention in one or more embodiments is advantageous positioned in providing effective storage within the vehicle interior, and in particular providing storage spaces that are lockable and/or not directly visible for enhanced storage security.

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second res

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

Abstract: In some embodiments, oxidants such as ozone (O3) and/or nitrous oxide (N2O) are used during the reactive sputtering of metal-based semiconductor layers used in TFT devices. The O3 and N2O gases are stronger oxidants and result in a decrease in the concentration of oxygen vacancies within the metal-based semiconductor layer. The decrease in the concentration of oxygen vacancies may result in improved stability under conditions of negative bias illumination stress (NBIS).

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second res