Patents by Inventor Charles A. Dark

Charles A. Dark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7989883
    Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: August 2, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, Andy Strachan
  • Patent number: 7776708
    Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. A composite layer stack is formed over the trench that has a nitride layer as a top layer. A plasma enhanced chemical vapor deposition (PECVD) oxide cap layer is formed over the nitride layer over the trench area. A mask and etch process is then applied to etch the composite layer stack adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied to protect the trench from unwanted effects of subsequent processing steps.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: August 17, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Charles A. Dark
  • Patent number: 7507607
    Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock, Jeffery L. Nilles, Andy Strachan
  • Patent number: 7488647
    Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: February 10, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, Andy Strachan
  • Patent number: 7470594
    Abstract: A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O2) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: December 30, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, Jr., William Max Coppock, Darren Lee Rust, Charles A. Dark
  • Patent number: 7118998
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock
  • Patent number: 6930010
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles A. Dark
  • Patent number: 6815797
    Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: November 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock, Jeffery L. Nilles, Andy Strachan
  • Patent number: 6815714
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles A. Dark
  • Patent number: 6812486
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 2, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock
  • Patent number: 6563189
    Abstract: The present invention provides a two-terminal Zener zap diode device structure that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flow of an aluminum alloy to create the current path. The use of oversized contacts in the diode structure permits the Tungsten plug to be eliminated from the diode structure and, thus, permits an aluminum alloy melt and flow mechanism to be used with a Tungsten plug process.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: May 13, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Charles Dark, William M. Coppock
  • Patent number: 6440781
    Abstract: A three-terminal integrated circuit device structure is provided that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flowing of an aluminum/aluminum alloy to create the current path. The use of an oversized contact permits the Tungsten plug to be eliminated from the anti-fuse structure, but allows the aluminum melt and flow mechanism to be used with a Tungsten plug process.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: August 27, 2002
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles Dark
  • Patent number: 6179975
    Abstract: In the monitoring of the consumption of a target of, for example, titanium for providing titanium and/or titanium nitride film, the process work in kilowatt-hours (Y1) is determined for complete consumption of the target when providing only titanium, and the process work in kilowatt-hours (Y2) is also determined for complete consumption of the target in providing only titanium nitride.
    Type: Grant
    Filed: October 2, 1996
    Date of Patent: January 30, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Charles A. Dark