Abstract: Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal is used to define a “frame” consisting of a predetermined number of clock periods, and a reset signal is used to define a larger period consisting of a predetermined number of frames. Due to a variety of system parameters, the innate delay time associated with each respective timing distribution path may differ. The system is operable to adjust the timing signals propagated to the plurality of host devices along each respective timing distribution path to compensate for these differences so that each host device remains synchronized with all other host devices.

Abstract: Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal is used to define a “frame” consisting of a predetermined number of clock periods, and a reset signal is used to define a larger period consisting of a predetermined number of frames. Due to a variety of system parameters, the innate delay time associated with each respective timing distribution path may differ. The system is operable to adjust the timing signals propagated to the plurality of host devices along each respective timing distribution path to compensate for these differences so that each host device remains synchronized with all other host devices.

Abstract: A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor.

Abstract: A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor.

Abstract: A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor.

Abstract: A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor.

Abstract: A power bus digital communication system reduces power and signal cabling in a space satellite by transformer coupling digital signal sources to power bus circuits, the transformer coupling devices in all power bus circuits being in parallel relation and electrically isolated from a power supply whereby the digital communication sources may communicate among themselves at a DC power level using a square wave modulated according to a Manchester code.

Abstract: A distributed data processing system is disclosed which has truly distributed control. A plurality of bus interface units (BIU) are interconnected by the distributed system data bus (DSDB) which includes a clock line, a serial command line (CMD), a serial bus allocation line (BAL) and a two byte wide data bus. A central clock connected to the clock line which defines the message frame timing, is the only centralized "control" element in the system. Each BIU may in turn be connected to either one or several data processing units, an I/O port, or a bridge connecting to still another similar bus network.

Abstract: A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller.A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput.A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor.A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.