Abstract: A method and apparatus for inspecting the surface of articles and subsequent grading of fruit. The apparatus includes conveying means for conveying an article through an inspection site and rotating the article about a lateral axis of the conveying means as it passes through the inspection site. The conveying means is arranged to convey the article with its longitudinal axis aligned with the longitudinal axis of the conveying means, the total angle of rotation about the lateral axis being limited to substantially 180 degrees. An imaging system has at least one image capture means and image directing means arranged to provide to the image capture means a plurality of different views of the inspection site about the lateral axis of the conveying means. The image capture means is arranged to capture a plurality of images of the article at different rotational angles as it passes through the inspection site.

Abstract: A level-shifter circuit capable of operating at low voltages. Two complementary current paths are provided between each of two intermediate nodes (at least one of which being an output node) and one of the supply voltages. A network of field-effect transistors are coupled between the other voltage supply and the intermediate nodes. The transistors include a pull-up (or pull-down as the case may be) transistor pair coupled to the high (or low as the case may be) voltage supply. There are two cascode transistor pairs coupled between the pull-up (or down) transistors and the corresponding intermediate node. One cascode pair couples the respective intermediate node to the drain terminal of the respective pull-up (or down) transistor. The other cascoded pair cross-couples the intermediate node to the gate terminal of the opposite pull-up (or down) transistor.

Abstract: A hinge which includes a gas strut. The hinge in one embodiment further includes a first control arm and a second control arm which is coupled to the first control arm. The gas strut in this one embodiment is coupled to both first and second control arms.

Abstract: Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.

Abstract: A multiple-purpose scarf which may be worn draped around the neck which in some embodiments includes one or more pockets. Game items such as programs, ticket stubs, and binoculars can be kept in pockets for ready access. It is contemplated that readable matter and/or a graphics may be located at one or more ends of the article of clothing facing away from wearer. Alternatively, or in addition, readable matter may be included on the inverse side of the scarf and may be displayed by holding the scarf above the wearer's head. One or more hand grasping elements may be provided along the scarf to aid the user in raising the scarf above the wearer's head. A hood may be included, which may be located within an envelope created within the center of the scarf. When not in use, the article of clothing may be rolled up and stuffed into one of the pockets, if desired.

Abstract: An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.

Abstract: Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.

Abstract: An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.