Abstract: The architecture and design method of an application specific processor having an instruction set which is matched to the needs of a specific application is provided. The application specific processor design method is based on using a library of pre-designed function blocks (111-113). These pre-designed function blocks encapsulate complex processing functions most commonly used by a specific application. Each of the pre-designed application specific function blocks is designed such that values of certain parameters of the encapsulated processing algorithm are implemented using registers which can be programmed with any desired value. Each of the pre-designed application specific function blocks is designed such that it can interface with a multi-purpose bus (110) through which the function block can accept invocation, reconfiguration, and data input/output routing commands.

Abstract: The architecture and design method of an application specific processor ("ASP") is disclosed. The ASP is designed by integrating selected pre-designed application elements contained in a library. These selected application elements can communicate with each other via a bus. Post-synthesis tailoring of the synthesized ASP is accomplished by using an instruction program which sequences the invocation of each application element and provides reconfiguration and data input/output routing commands thereto. A power management design is incorporated within the application elements allowing the majority of the application elements to be turned on only during periods of invocation.

Abstract: In a dual microprocessor system, a processor transfer, or swap, arrangement and method therefor are disclosed for transferring control from one processor to another. The present invention involves the temporary suspension of operation of a first microprocessor which relinquishes system control and the initiation of operation of a second microprocessor which may begin operation either where it last left off or may execute a new operating routine in accordance with instructions provided by the first microprocessor. Provision is made for automatically handing over system control to the second microprocessor upon the occurrence of an interrupt. In addition, the microprocessor not exercising system control is rendered unresponsive to the occurrence of a program interrupt allowing it to continue opration unaffected by the program interrupt following its reactivation.

Abstract: In a video display system having a video random access memory (RAM) including a plurality of color memory banks, with one memory bank for each of the primary colors, provision is made for simultaneously writing to all of the color banks. A central processor unit (CPU) places data onto the system bus and asserts WRT-R, WRT-G and/or WRT-B signals in selectively writing at the same time to any or all of the video RAM banks, where the primary colors are red, green and blue. Logic circuitry coupled to the three RAM banks then gates designated Row and Column Address Strobe (RAS and CAS) signals to each of the color arrays followed by color video data signals. The time required to thus write video display information into the multi-bank video RAM array is thus reduced and system video data throughput correspondingly increased.

Abstract: A multi-key keyboard is scanned at high speed in such a manner as to substantially reduce erroneous key entries caused by the simultaneous engagement of more than one key. A keyboard processor determines which key is down by sequential scanning of the keyboard, encodes the selected key and sends this code to a master processor, or CPU. A 2-key lockout scanning approach is employed wherein keyboard scanning stops when two keys are selected simultaneously. Scanning is resumed when either one or both of the first two keys are released. By limiting simultaneous key engagement detection to two keys, system complexity and cost are kept within reasonable limits while insuring against erroneous key entries. Detecting and storing the key engagement sequence permits a selected special function, e.g., automatic key repeat, to be applied to the last selected key rather than to an earlier selected, but simultaneously engaged, key.

Abstract: A video display system utilizes three banks of memory for producing an 8-color or an 8-level gray scale display. A separate memory plane, or random access memory (RAM) array, for each of the "primary" video colors, i.e., red, green and blue, is used in a bit-mapped video graphics implementation for a computer driven video display. In a monochrome display, pixel mixing produces the 8-level gray scale display. Each of the video planes may be selectively disabled as desired for special applications. For example, a limited animation capability may be provided by displaying one page while generating a new page in a non-displayed page. By disabling the currently displayed plane as the new plane is enabled, instantaneous page modification may be closely simulated for animated applications. The thus disabled video plane may then be used as any normal page of RAM for any other application.